Lines Matching refs:dws
50 struct dw_spi *dws = file->private_data; in dw_spi_show_regs() local
60 "%s registers:\n", dev_name(&dws->master->dev)); in dw_spi_show_regs()
64 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); in dw_spi_show_regs()
66 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); in dw_spi_show_regs()
68 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); in dw_spi_show_regs()
70 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); in dw_spi_show_regs()
72 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); in dw_spi_show_regs()
74 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); in dw_spi_show_regs()
76 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); in dw_spi_show_regs()
78 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); in dw_spi_show_regs()
80 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); in dw_spi_show_regs()
82 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); in dw_spi_show_regs()
84 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); in dw_spi_show_regs()
86 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); in dw_spi_show_regs()
88 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); in dw_spi_show_regs()
90 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); in dw_spi_show_regs()
92 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); in dw_spi_show_regs()
108 static int dw_spi_debugfs_init(struct dw_spi *dws) in dw_spi_debugfs_init() argument
110 dws->debugfs = debugfs_create_dir("dw_spi", NULL); in dw_spi_debugfs_init()
111 if (!dws->debugfs) in dw_spi_debugfs_init()
115 dws->debugfs, (void *)dws, &dw_spi_regs_ops); in dw_spi_debugfs_init()
119 static void dw_spi_debugfs_remove(struct dw_spi *dws) in dw_spi_debugfs_remove() argument
121 debugfs_remove_recursive(dws->debugfs); in dw_spi_debugfs_remove()
125 static inline int dw_spi_debugfs_init(struct dw_spi *dws) in dw_spi_debugfs_init() argument
130 static inline void dw_spi_debugfs_remove(struct dw_spi *dws) in dw_spi_debugfs_remove() argument
137 struct dw_spi *dws = spi_master_get_devdata(spi->master); in dw_spi_set_cs() local
145 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); in dw_spi_set_cs()
149 static inline u32 tx_max(struct dw_spi *dws) in tx_max() argument
153 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; in tx_max()
154 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); in tx_max()
164 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) in tx_max()
165 / dws->n_bytes; in tx_max()
167 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); in tx_max()
171 static inline u32 rx_max(struct dw_spi *dws) in rx_max() argument
173 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; in rx_max()
175 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); in rx_max()
178 static void dw_writer(struct dw_spi *dws) in dw_writer() argument
180 u32 max = tx_max(dws); in dw_writer()
185 if (dws->tx_end - dws->len) { in dw_writer()
186 if (dws->n_bytes == 1) in dw_writer()
187 txw = *(u8 *)(dws->tx); in dw_writer()
189 txw = *(u16 *)(dws->tx); in dw_writer()
191 dw_write_io_reg(dws, DW_SPI_DR, txw); in dw_writer()
192 dws->tx += dws->n_bytes; in dw_writer()
196 static void dw_reader(struct dw_spi *dws) in dw_reader() argument
198 u32 max = rx_max(dws); in dw_reader()
202 rxw = dw_read_io_reg(dws, DW_SPI_DR); in dw_reader()
204 if (dws->rx_end - dws->len) { in dw_reader()
205 if (dws->n_bytes == 1) in dw_reader()
206 *(u8 *)(dws->rx) = rxw; in dw_reader()
208 *(u16 *)(dws->rx) = rxw; in dw_reader()
210 dws->rx += dws->n_bytes; in dw_reader()
214 static void int_error_stop(struct dw_spi *dws, const char *msg) in int_error_stop() argument
216 spi_reset_chip(dws); in int_error_stop()
218 dev_err(&dws->master->dev, "%s\n", msg); in int_error_stop()
219 dws->master->cur_msg->status = -EIO; in int_error_stop()
220 spi_finalize_current_transfer(dws->master); in int_error_stop()
223 static irqreturn_t interrupt_transfer(struct dw_spi *dws) in interrupt_transfer() argument
225 u16 irq_status = dw_readl(dws, DW_SPI_ISR); in interrupt_transfer()
229 dw_readl(dws, DW_SPI_ICR); in interrupt_transfer()
230 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); in interrupt_transfer()
234 dw_reader(dws); in interrupt_transfer()
235 if (dws->rx_end == dws->rx) { in interrupt_transfer()
236 spi_mask_intr(dws, SPI_INT_TXEI); in interrupt_transfer()
237 spi_finalize_current_transfer(dws->master); in interrupt_transfer()
241 spi_mask_intr(dws, SPI_INT_TXEI); in interrupt_transfer()
242 dw_writer(dws); in interrupt_transfer()
244 spi_umask_intr(dws, SPI_INT_TXEI); in interrupt_transfer()
253 struct dw_spi *dws = spi_master_get_devdata(master); in dw_spi_irq() local
254 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; in dw_spi_irq()
260 spi_mask_intr(dws, SPI_INT_TXEI); in dw_spi_irq()
264 return dws->transfer_handler(dws); in dw_spi_irq()
268 static int poll_transfer(struct dw_spi *dws) in poll_transfer() argument
271 dw_writer(dws); in poll_transfer()
272 dw_reader(dws); in poll_transfer()
274 } while (dws->rx_end > dws->rx); in poll_transfer()
282 struct dw_spi *dws = spi_master_get_devdata(master); in dw_spi_transfer_one() local
290 dws->dma_mapped = 0; in dw_spi_transfer_one()
292 dws->tx = (void *)transfer->tx_buf; in dw_spi_transfer_one()
293 dws->tx_end = dws->tx + transfer->len; in dw_spi_transfer_one()
294 dws->rx = transfer->rx_buf; in dw_spi_transfer_one()
295 dws->rx_end = dws->rx + transfer->len; in dw_spi_transfer_one()
296 dws->len = transfer->len; in dw_spi_transfer_one()
298 spi_enable_chip(dws, 0); in dw_spi_transfer_one()
303 clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe; in dw_spi_transfer_one()
308 spi_set_clk(dws, chip->clk_div); in dw_spi_transfer_one()
311 dws->n_bytes = 1; in dw_spi_transfer_one()
312 dws->dma_width = 1; in dw_spi_transfer_one()
314 dws->n_bytes = 2; in dw_spi_transfer_one()
315 dws->dma_width = 2; in dw_spi_transfer_one()
330 if (dws->rx && dws->tx) in dw_spi_transfer_one()
332 else if (dws->rx) in dw_spi_transfer_one()
341 dw_writel(dws, DW_SPI_CTRL0, cr0); in dw_spi_transfer_one()
345 dws->dma_mapped = master->cur_msg_mapped; in dw_spi_transfer_one()
348 spi_mask_intr(dws, 0xff); in dw_spi_transfer_one()
354 if (dws->dma_mapped) { in dw_spi_transfer_one()
355 ret = dws->dma_ops->dma_setup(dws, transfer); in dw_spi_transfer_one()
357 spi_enable_chip(dws, 1); in dw_spi_transfer_one()
361 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); in dw_spi_transfer_one()
362 dw_writel(dws, DW_SPI_TXFLTR, txlevel); in dw_spi_transfer_one()
367 spi_umask_intr(dws, imask); in dw_spi_transfer_one()
369 dws->transfer_handler = interrupt_transfer; in dw_spi_transfer_one()
372 spi_enable_chip(dws, 1); in dw_spi_transfer_one()
374 if (dws->dma_mapped) { in dw_spi_transfer_one()
375 ret = dws->dma_ops->dma_transfer(dws, transfer); in dw_spi_transfer_one()
381 return poll_transfer(dws); in dw_spi_transfer_one()
389 struct dw_spi *dws = spi_master_get_devdata(master); in dw_spi_handle_err() local
391 if (dws->dma_mapped) in dw_spi_handle_err()
392 dws->dma_ops->dma_stop(dws); in dw_spi_handle_err()
394 spi_reset_chip(dws); in dw_spi_handle_err()
449 static void spi_hw_init(struct device *dev, struct dw_spi *dws) in spi_hw_init() argument
451 spi_reset_chip(dws); in spi_hw_init()
457 if (!dws->fifo_len) { in spi_hw_init()
461 dw_writel(dws, DW_SPI_TXFLTR, fifo); in spi_hw_init()
462 if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) in spi_hw_init()
465 dw_writel(dws, DW_SPI_TXFLTR, 0); in spi_hw_init()
467 dws->fifo_len = (fifo == 1) ? 0 : fifo; in spi_hw_init()
468 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); in spi_hw_init()
472 int dw_spi_add_host(struct device *dev, struct dw_spi *dws) in dw_spi_add_host() argument
477 BUG_ON(dws == NULL); in dw_spi_add_host()
483 dws->master = master; in dw_spi_add_host()
484 dws->type = SSI_MOTO_SPI; in dw_spi_add_host()
485 dws->dma_inited = 0; in dw_spi_add_host()
486 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); in dw_spi_add_host()
487 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); in dw_spi_add_host()
489 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master); in dw_spi_add_host()
497 master->bus_num = dws->bus_num; in dw_spi_add_host()
498 master->num_chipselect = dws->num_cs; in dw_spi_add_host()
504 master->max_speed_hz = dws->max_freq; in dw_spi_add_host()
508 spi_hw_init(dev, dws); in dw_spi_add_host()
510 if (dws->dma_ops && dws->dma_ops->dma_init) { in dw_spi_add_host()
511 ret = dws->dma_ops->dma_init(dws); in dw_spi_add_host()
514 dws->dma_inited = 0; in dw_spi_add_host()
516 master->can_dma = dws->dma_ops->can_dma; in dw_spi_add_host()
520 spi_master_set_devdata(master, dws); in dw_spi_add_host()
527 dw_spi_debugfs_init(dws); in dw_spi_add_host()
531 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_add_host()
532 dws->dma_ops->dma_exit(dws); in dw_spi_add_host()
533 spi_enable_chip(dws, 0); in dw_spi_add_host()
534 free_irq(dws->irq, master); in dw_spi_add_host()
541 void dw_spi_remove_host(struct dw_spi *dws) in dw_spi_remove_host() argument
543 dw_spi_debugfs_remove(dws); in dw_spi_remove_host()
545 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_remove_host()
546 dws->dma_ops->dma_exit(dws); in dw_spi_remove_host()
548 spi_shutdown_chip(dws); in dw_spi_remove_host()
550 free_irq(dws->irq, dws->master); in dw_spi_remove_host()
554 int dw_spi_suspend_host(struct dw_spi *dws) in dw_spi_suspend_host() argument
558 ret = spi_master_suspend(dws->master); in dw_spi_suspend_host()
562 spi_shutdown_chip(dws); in dw_spi_suspend_host()
567 int dw_spi_resume_host(struct dw_spi *dws) in dw_spi_resume_host() argument
571 spi_hw_init(&dws->master->dev, dws); in dw_spi_resume_host()
572 ret = spi_master_resume(dws->master); in dw_spi_resume_host()
574 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); in dw_spi_resume_host()