159 	bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);  in bfin_spi_flush()
207 	bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);  in bfin_spi_restore_state()
214 	bfin_write(&drv_data->regs->ctl, chip->ctl_reg);  in bfin_spi_restore_state()
215 	bfin_write(&drv_data->regs->baud, chip->baud);  in bfin_spi_restore_state()
233 		bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));  in bfin_spi_u8_writer()
251 		bfin_write(&drv_data->regs->tdbr, tx_val);  in bfin_spi_u8_reader()
264 		bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));  in bfin_spi_u8_duplex()
283 		bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));  in bfin_spi_u16_writer()
302 		bfin_write(&drv_data->regs->tdbr, tx_val);  in bfin_spi_u16_reader()
316 		bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));  in bfin_spi_u16_duplex()
429 				bfin_write(&drv_data->regs->tdbr, *buf2++);  in bfin_spi_pio_irq_handler()
436 				bfin_write(&drv_data->regs->tdbr, *buf2++);  in bfin_spi_pio_irq_handler()
446 				bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);  in bfin_spi_pio_irq_handler()
452 				bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);  in bfin_spi_pio_irq_handler()
462 				bfin_write(&drv_data->regs->tdbr, *buf++);  in bfin_spi_pio_irq_handler()
468 				bfin_write(&drv_data->regs->tdbr, *buf++);  in bfin_spi_pio_irq_handler()
498 		bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */  in bfin_spi_dma_irq_handler()
499 		bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */  in bfin_spi_dma_irq_handler()
500 		bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */  in bfin_spi_dma_irq_handler()
655 	bfin_write(&drv_data->regs->ctl, cr);  in bfin_spi_pump_transfers()
664 	bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));  in bfin_spi_pump_transfers()
666 	bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);  in bfin_spi_pump_transfers()
716 			bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);  in bfin_spi_pump_transfers()
771 		bfin_write(&drv_data->regs->ctl, cr);  in bfin_spi_pump_transfers()
785 	bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);  in bfin_spi_pump_transfers()
795 			bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);  in bfin_spi_pump_transfers()
802 					bfin_write(&drv_data->regs->tdbr, *buf++);  in bfin_spi_pump_transfers()
807 					bfin_write(&drv_data->regs->tdbr, *buf++);  in bfin_spi_pump_transfers()
1339 	bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);  in bfin_spi_probe()
1340 	bfin_write(&drv_data->regs->flg, 0xFF00);  in bfin_spi_probe()
1418 	bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);  in bfin_spi_suspend()
1419 	bfin_write(&drv_data->regs->flg, 0xFF00);  in bfin_spi_suspend()
1429 	bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);  in bfin_spi_resume()
1430 	bfin_write(&drv_data->regs->flg, drv_data->flag_reg);  in bfin_spi_resume()