168 static void tegra_pmc_writel(u32 value, unsigned long offset)  in tegra_pmc_writel()  argument
170 	writel(value, pmc->base + offset);  in tegra_pmc_writel()
386 	u32 value;  in tegra_pmc_restart_notify()  local
388 	value = tegra_pmc_readl(PMC_SCRATCH0);  in tegra_pmc_restart_notify()
389 	value &= ~PMC_SCRATCH0_MODE_MASK;  in tegra_pmc_restart_notify()
393 			value |= PMC_SCRATCH0_MODE_RECOVERY;  in tegra_pmc_restart_notify()
396 			value |= PMC_SCRATCH0_MODE_BOOTLOADER;  in tegra_pmc_restart_notify()
399 			value |= PMC_SCRATCH0_MODE_RCM;  in tegra_pmc_restart_notify()
402 	tegra_pmc_writel(value, PMC_SCRATCH0);  in tegra_pmc_restart_notify()
404 	value = tegra_pmc_readl(0);  in tegra_pmc_restart_notify()
405 	value |= 0x10;  in tegra_pmc_restart_notify()
406 	tegra_pmc_writel(value, 0);  in tegra_pmc_restart_notify()
461 	unsigned long rate, value;  in tegra_io_rail_prepare()  local
485 	value = DIV_ROUND_UP(1000000000, rate);  in tegra_io_rail_prepare()
486 	value = DIV_ROUND_UP(200, value);  in tegra_io_rail_prepare()
487 	tegra_pmc_writel(value, SEL_DPD_TIM);  in tegra_io_rail_prepare()
495 	unsigned long value;  in tegra_io_rail_poll()  local
500 		value = tegra_pmc_readl(offset);  in tegra_io_rail_poll()
501 		if ((value & mask) == val)  in tegra_io_rail_poll()
517 	unsigned long request, status, value;  in tegra_io_rail_power_on()  local
527 	value = tegra_pmc_readl(request);  in tegra_io_rail_power_on()
528 	value |= mask;  in tegra_io_rail_power_on()
529 	value &= ~IO_DPD_REQ_CODE_MASK;  in tegra_io_rail_power_on()
530 	value |= IO_DPD_REQ_CODE_OFF;  in tegra_io_rail_power_on()
531 	tegra_pmc_writel(value, request);  in tegra_io_rail_power_on()
547 	unsigned long request, status, value;  in tegra_io_rail_power_off()  local
559 	value = tegra_pmc_readl(request);  in tegra_io_rail_power_off()
560 	value |= mask;  in tegra_io_rail_power_off()
561 	value &= ~IO_DPD_REQ_CODE_MASK;  in tegra_io_rail_power_off()
562 	value |= IO_DPD_REQ_CODE_ON;  in tegra_io_rail_power_off()
563 	tegra_pmc_writel(value, request);  in tegra_io_rail_power_off()
592 	u32 value;  in tegra_pmc_enter_suspend_mode()  local
626 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
627 	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;  in tegra_pmc_enter_suspend_mode()
628 	value |= PMC_CNTRL_CPU_PWRREQ_OE;  in tegra_pmc_enter_suspend_mode()
629 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
635 	u32 value, values[2];  in tegra_pmc_parse_dt()  local
637 	if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {  in tegra_pmc_parse_dt()
639 		switch (value) {  in tegra_pmc_parse_dt()
660 	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))  in tegra_pmc_parse_dt()
663 	pmc->cpu_good_time = value;  in tegra_pmc_parse_dt()
665 	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))  in tegra_pmc_parse_dt()
668 	pmc->cpu_off_time = value;  in tegra_pmc_parse_dt()
677 	if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))  in tegra_pmc_parse_dt()
680 	pmc->core_off_time = value;  in tegra_pmc_parse_dt()
707 	u32 value;  in tegra_pmc_init()  local
710 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
711 	value |= PMC_CNTRL_CPU_PWRREQ_OE;  in tegra_pmc_init()
712 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
714 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
717 		value &= ~PMC_CNTRL_SYSCLK_POLARITY;  in tegra_pmc_init()
719 		value |= PMC_CNTRL_SYSCLK_POLARITY;  in tegra_pmc_init()
722 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
725 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_init()
726 	value |= PMC_CNTRL_SYSCLK_OE;  in tegra_pmc_init()
727 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_init()
736 	u32 value, checksum;  in tegra_pmc_init_tsense_reset()  local
770 	value = tegra_pmc_readl(PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
771 	value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;  in tegra_pmc_init_tsense_reset()
772 	tegra_pmc_writel(value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
774 	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |  in tegra_pmc_init_tsense_reset()
776 	tegra_pmc_writel(value, PMC_SCRATCH54);  in tegra_pmc_init_tsense_reset()
778 	value = PMC_SCRATCH55_RESET_TEGRA;  in tegra_pmc_init_tsense_reset()
779 	value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;  in tegra_pmc_init_tsense_reset()
780 	value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;  in tegra_pmc_init_tsense_reset()
781 	value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;  in tegra_pmc_init_tsense_reset()
787 	checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)  in tegra_pmc_init_tsense_reset()
788 		+ ((value >> 24) & 0xff);  in tegra_pmc_init_tsense_reset()
792 	value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;  in tegra_pmc_init_tsense_reset()
794 	tegra_pmc_writel(value, PMC_SCRATCH55);  in tegra_pmc_init_tsense_reset()
796 	value = tegra_pmc_readl(PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
797 	value |= PMC_SENSOR_CTRL_ENABLE_RST;  in tegra_pmc_init_tsense_reset()
798 	tegra_pmc_writel(value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
1084 	u32 value;  in tegra_pmc_early_init()  local
1140 	value = tegra_pmc_readl(PMC_CNTRL);  in tegra_pmc_early_init()
1143 		value |= PMC_CNTRL_INTR_POLARITY;  in tegra_pmc_early_init()
1145 		value &= ~PMC_CNTRL_INTR_POLARITY;  in tegra_pmc_early_init()
1147 	tegra_pmc_writel(value, PMC_CNTRL);  in tegra_pmc_early_init()