228 	struct irq_chip_generic *gc = pmu->irq_gc;  in pmu_irq_handler()  local
230 	void __iomem *base = gc->reg_base;  in pmu_irq_handler()
231 	u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;  in pmu_irq_handler()
259 	irq_gc_lock(gc);  in pmu_irq_handler()
262 	irq_gc_unlock(gc);  in pmu_irq_handler()
268 	struct irq_chip_generic *gc;  in dove_init_pmu_irq()  local
293 	gc = irq_get_domain_generic_chip(domain, 0);  in dove_init_pmu_irq()
294 	gc->reg_base = pmu->pmc_base;  in dove_init_pmu_irq()
295 	gc->chip_types[0].regs.mask = PMC_IRQ_MASK;  in dove_init_pmu_irq()
296 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;  in dove_init_pmu_irq()
297 	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;  in dove_init_pmu_irq()
300 	pmu->irq_gc = gc;  in dove_init_pmu_irq()