32 #define dma_write32(VAL, REG) \  macro
274 		dma_write32(val | DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
275 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
279 		dma_write32(DMA_RESET_FAS366, DMA_CSR);  in sbus_esp_reset_dma()
280 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
309 		dma_write32(0, DMA_CSR);  in sbus_esp_reset_dma()
310 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_reset_dma()
312 		dma_write32(0, DMA_ADDR);  in sbus_esp_reset_dma()
318 			dma_write32(val | DMA_3CLKS, DMA_CSR);  in sbus_esp_reset_dma()
330 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
342 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
351 	dma_write32(val | DMA_INT_ENAB, DMA_CSR);  in sbus_esp_reset_dma()
367 		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);  in sbus_esp_dma_drain()
383 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_dma_invalidate()
390 		dma_write32(0, DMA_CSR);  in sbus_esp_dma_invalidate()
391 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_dma_invalidate()
396 		dma_write32(0, DMA_ADDR);  in sbus_esp_dma_invalidate()
413 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
415 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
442 		dma_write32(dma_count, DMA_COUNT);  in sbus_esp_send_dma_cmd()
443 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
444 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
452 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
455 			dma_write32(end - addr, DMA_COUNT);  in sbus_esp_send_dma_cmd()
457 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
538 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in esp_sbus_probe_one()
598 	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);  in esp_sbus_remove()