Lines Matching refs:mmio_base
296 void __iomem *mmio_base; /* iomapped PCI memory space */ member
503 writel(hba->req_head, hba->mmio_base + IMR0); in stex_send_cmd()
504 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); in stex_send_cmd()
505 readl(hba->mmio_base + IDBL); /* flush */ in stex_send_cmd()
533 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); in stex_ss_send_cmd()
534 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ in stex_ss_send_cmd()
535 writel(addr, hba->mmio_base + YH2I_REQ); in stex_ss_send_cmd()
536 readl(hba->mmio_base + YH2I_REQ); /* flush */ in stex_ss_send_cmd()
746 void __iomem *base = hba->mmio_base; in stex_mu_intr()
834 void __iomem *base = hba->mmio_base; in stex_intr()
935 void __iomem *base = hba->mmio_base; in stex_ss_intr()
959 void __iomem *base = hba->mmio_base; in stex_common_handshake()
1043 void __iomem *base = hba->mmio_base; in stex_ss_handshake()
1142 base = hba->mmio_base; in stex_abort()
1228 base = hba->mmio_base; in stex_yos_reset()
1255 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); in stex_ss_reset()
1256 readl(hba->mmio_base + YH2I_INT); in stex_ss_reset()
1546 hba->mmio_base = pci_ioremap_bar(pdev, 0); in stex_probe()
1547 if ( !hba->mmio_base) { in stex_probe()
1677 iounmap(hba->mmio_base); in stex_probe()
1740 iounmap(hba->mmio_base); in stex_hba_free()