1370 	uint64_t off8, val, mem_crb, word[2] = {0, 0};  in qla4_82xx_pci_mem_read_2M()  local
1377 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_read_2M()
1379 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_read_2M()
1397 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_read_2M()
1399 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_read_2M()
1401 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1403 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1406 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_read_2M()
1422 				mem_crb + MIU_TEST_AGT_RDDATA(k));  in qla4_82xx_pci_mem_read_2M()
1461 	uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};  in qla4_82xx_pci_mem_write_2M()  local
1467 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_write_2M()
1469 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_write_2M()
1522 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1524 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1526 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1528 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1530 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,  in qla4_82xx_pci_mem_write_2M()
1533 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,  in qla4_82xx_pci_mem_write_2M()
1537 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1539 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1542 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_write_2M()