1142 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_unprotect_flash()
1143 	    RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_unprotect_flash()
1144 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_unprotect_flash()
1181 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_protect_flash()
1182 	    RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_protect_flash()
1183 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_protect_flash()
1409 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1410 	    RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1411 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1434 	WRT_REG_DWORD(&reg->ctrl_status,  in qla24xx_write_nvram_data()
1435 	    RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);  in qla24xx_write_nvram_data()
1436 	RD_REG_DWORD(&reg->ctrl_status);	/* PCI Posting. */  in qla24xx_write_nvram_data()
1907 	data = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_flash_enable()
1909 	WRT_REG_WORD(&reg->ctrl_status, data);  in qla2x00_flash_enable()
1910 	RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_enable()
1923 	data = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_flash_disable()
1925 	WRT_REG_WORD(&reg->ctrl_status, data);  in qla2x00_flash_disable()
1926 	RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_flash_disable()
1945 	bank_select = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_read_flash_byte()
1953 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
1954 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
1965 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
1966 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
1970 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_read_flash_byte()
1971 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_read_flash_byte()
2005 	bank_select = RD_REG_WORD(&reg->ctrl_status);  in qla2x00_write_flash_byte()
2012 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2013 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2016 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2018 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2026 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2027 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2031 		WRT_REG_WORD(&reg->ctrl_status, bank_select);  in qla2x00_write_flash_byte()
2032 		RD_REG_WORD(&reg->ctrl_status);	/* PCI Posting. */  in qla2x00_write_flash_byte()
2041 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2043 		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_write_flash_byte()
2335 	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);  in qla2x00_write_optrom_data()