Lines Matching refs:RD_REG_WORD
29 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()
32 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()
37 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
44 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
62 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_unlock_nvram_access()
77 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
81 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
84 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
124 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
127 reg_data = RD_REG_WORD(®->nvram); in qla2x00_nvram_request()
131 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
137 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
175 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_deselect()
220 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_write_nvram_word()
229 word = RD_REG_WORD(®->nvram); in qla2x00_write_nvram_word()
279 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_write_nvram_word_tmo()
282 word = RD_REG_WORD(®->nvram); in qla2x00_write_nvram_word_tmo()
351 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_clear_nvram_protection()
360 word = RD_REG_WORD(®->nvram); in qla2x00_clear_nvram_protection()
411 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_set_nvram_protection()
420 word = RD_REG_WORD(®->nvram); in qla2x00_set_nvram_protection()
1529 gpio_enable = RD_REG_WORD(®->gpioe); in qla2x00_beacon_blink()
1530 gpio_data = RD_REG_WORD(®->gpiod); in qla2x00_beacon_blink()
1540 RD_REG_WORD(®->gpioe); in qla2x00_beacon_blink()
1556 RD_REG_WORD(®->gpiod); in qla2x00_beacon_blink()
1586 gpio_enable = RD_REG_WORD(®->gpioe); in qla2x00_beacon_on()
1587 gpio_data = RD_REG_WORD(®->gpiod); in qla2x00_beacon_on()
1596 RD_REG_WORD(®->gpioe); in qla2x00_beacon_on()
1605 RD_REG_WORD(®->gpiod); in qla2x00_beacon_on()
1907 data = RD_REG_WORD(®->ctrl_status); in qla2x00_flash_enable()
1910 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_flash_enable()
1923 data = RD_REG_WORD(®->ctrl_status); in qla2x00_flash_disable()
1926 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_flash_disable()
1945 bank_select = RD_REG_WORD(®->ctrl_status); in qla2x00_read_flash_byte()
1954 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
1957 data = RD_REG_WORD(®->flash_data); in qla2x00_read_flash_byte()
1966 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
1971 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
2005 bank_select = RD_REG_WORD(®->ctrl_status); in qla2x00_write_flash_byte()
2013 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2016 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2018 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2027 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2032 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2041 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2043 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2226 RD_REG_WORD(®->nvram); in qla2x00_read_flash_data()
2230 RD_REG_WORD(®->nvram); in qla2x00_read_flash_data()
2256 RD_REG_WORD(®->hccr); in qla2x00_suspend_hba()
2259 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
2299 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_read_optrom_data()
2303 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_read_optrom_data()
2484 RD_REG_WORD(®->nvram); in qla2x00_write_optrom_data()