806 		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);  in qla2300_pci_config()
808 			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
829 		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);  in qla2300_pci_config()
831 			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
993 		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);  in qla2x00_reset_chip()
996 				if ((RD_REG_WORD(&reg->hccr) &  in qla2x00_reset_chip()
1002 			RD_REG_WORD(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
1044 		WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_chip()
1045 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
1048 		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_chip()
1049 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
1052 	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);  in qla2x00_reset_chip()
1053 	WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);  in qla2x00_reset_chip()
1076 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_chip()
1081 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_chip()
1082 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
1100 		WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);  in qla2x00_reset_chip()
1101 		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
1156 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1182 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1200 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1220 	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);  in qla24xx_reset_risc()
1221 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1223 	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);  in qla24xx_reset_risc()
1224 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1226 	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);  in qla24xx_reset_risc()
1227 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1243 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1290 	WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);  in qla25xx_manipulate_risc_semaphore()
1410 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_chip_diag()
1411 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_chip_diag()
1827 		WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));  in qla2x00_setup_chip()
1828 		RD_REG_WORD(&reg->hccr);  in qla2x00_setup_chip()
1899 			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);  in qla2x00_setup_chip()
1902 			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);  in qla2x00_setup_chip()
1903 		RD_REG_WORD(&reg->hccr);  in qla2x00_setup_chip()
2166 	RD_REG_DWORD(&ioreg->hccr);  in qla24xx_config_rings()
5014 	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_adapter()
5015 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
5016 	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_adapter()
5017 	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
5035 	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);  in qla24xx_reset_adapter()
5036 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()
5037 	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);  in qla24xx_reset_adapter()
5038 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()