Lines Matching refs:BIT_5
66 #define BIT_5 0x20 macro
307 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
540 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
843 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
864 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1014 #define MBX_5 BIT_5
1548 #define CF_READ BIT_5
1643 #define PO_DISABLE_INCR_REF_TAG BIT_5
1732 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
3072 #define DT_ISP6312 BIT_5
3555 #define DFLG_DEV_FAILED BIT_5