Lines Matching refs:uint16_t
125 uint16_t id_l; /* ID low */
126 uint16_t id_h; /* ID high */
127 uint16_t cfg_0; /* Configuration 0 */
135 uint16_t cfg_1; /* Configuration 1 */
142 uint16_t ictrl; /* Interface control */
148 uint16_t istatus; /* Interface status */
152 uint16_t semaphore; /* Semaphore */
153 uint16_t nvram; /* NVRAM register. */
159 uint16_t flash_data; /* Flash BIOS data */
160 uint16_t flash_address; /* Flash BIOS address */
162 uint16_t unused_1[0x06];
165 uint16_t cdma_cfg;
170 uint16_t cdma_ctrl;
171 uint16_t cdma_status;
172 uint16_t cdma_fifo_status;
173 uint16_t cdma_count;
174 uint16_t cdma_reserved;
175 uint16_t cdma_address_count_0;
176 uint16_t cdma_address_count_1;
177 uint16_t cdma_address_count_2;
178 uint16_t cdma_address_count_3;
180 uint16_t unused_2[0x06];
182 uint16_t ddma_cfg;
187 uint16_t ddma_ctrl;
188 uint16_t ddma_status;
189 uint16_t ddma_fifo_status;
190 uint16_t ddma_xfer_count_low;
191 uint16_t ddma_xfer_count_high;
192 uint16_t ddma_addr_count_0;
193 uint16_t ddma_addr_count_1;
194 uint16_t ddma_addr_count_2;
195 uint16_t ddma_addr_count_3;
197 uint16_t unused_3[0x0e];
199 uint16_t mailbox0; /* Mailbox 0 */
200 uint16_t mailbox1; /* Mailbox 1 */
201 uint16_t mailbox2; /* Mailbox 2 */
202 uint16_t mailbox3; /* Mailbox 3 */
203 uint16_t mailbox4; /* Mailbox 4 */
204 uint16_t mailbox5; /* Mailbox 5 */
205 uint16_t mailbox6; /* Mailbox 6 */
206 uint16_t mailbox7; /* Mailbox 7 */
208 uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
210 uint16_t host_cmd; /* Host command and control */
214 uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
216 uint16_t gpio_data;
217 uint16_t gpio_enable;
219 uint16_t unused_6[0x11]; /* d0-f0 */
220 uint16_t scsiControlPins; /* f2 */
374 uint16_t unused_8; /* 8, 9 */
375 uint16_t unused_10; /* 10, 11 */
376 uint16_t unused_12; /* 12, 13 */
377 uint16_t unused_14; /* 14, 15 */
398 uint16_t isp_parameter; /* 18, 19 */
401 uint16_t w;
403 uint16_t enable_fast_posting:1;
404 uint16_t report_lvd_bus_transition:1;
405 uint16_t unused_2:1;
406 uint16_t unused_3:1;
407 uint16_t disable_iosbs_with_bus_reset_status:1;
408 uint16_t disable_synchronous_backoff:1;
409 uint16_t unused_6:1;
410 uint16_t synchronous_backoff_reporting:1;
411 uint16_t disable_reselection_fairness:1;
412 uint16_t unused_9:1;
413 uint16_t unused_10:1;
414 uint16_t unused_11:1;
415 uint16_t unused_12:1;
416 uint16_t unused_13:1;
417 uint16_t unused_14:1;
418 uint16_t unused_15:1;
422 uint16_t unused_22; /* 22, 23 */
447 uint16_t selection_timeout; /* 30, 31 */
448 uint16_t max_queue_depth; /* 32, 33 */
450 uint16_t unused_34; /* 34, 35 */
451 uint16_t unused_36; /* 36, 37 */
452 uint16_t unused_38; /* 38, 39 */
498 uint16_t unused_248; /* 248, 249 */
500 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
994 uint16_t device_enables; /* Device enable bits. */
995 uint16_t lun_disables; /* LUN disable bits. */
996 uint16_t qtag_enables; /* Tag queue enables. */
997 uint16_t hiwat; /* High water mark per device. */
1009 uint16_t sync_mask;
1010 uint16_t wide_mask;
1011 uint16_t ppr_mask;
1042 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1047 uint16_t req_ring_index; /* Current index. */
1048 uint16_t req_q_cnt; /* Number of available entries. */
1053 uint16_t rsp_ring_index; /* Current index. */