Lines Matching refs:u32
124 u32 tag_of_task_to_be_managed;
127 u32 signature;
158 u32 data_type;
161 u32 direct_len;
162 u32 direct_offset;
168 u32 direct_len;
172 u32 direct_len;
173 u32 direct_offset;
174 u32 read_len;
200 u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
214 struct pm8001_device *pm8001_dev, u32 flag);
215 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
217 u32 phy_id, u32 phy_op);
219 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
220 u32 cmd_tag);
228 struct pm8001_device *pm8001_dev, u32 state);
230 u32 state);
232 u32 state);
237 u32 encrypt;
238 u32 n_phy;
258 u32 phy_type;
260 u32 frame_rcvd_size;
271 u32 attached_phy;
272 u32 id;
275 u32 device_id;
276 u32 running_req;
294 u32 n_elem;
295 u32 ccb_tag;
306 u32 phys_addr_hi;
307 u32 phys_addr_lo;
308 u32 total_len;
309 u32 num_elements;
310 u32 element_size;
311 u32 alignment;
316 u32 count;
322 u32 cipher_mode;
323 u32 sec_mode;
324 u32 status;
325 u32 flag;
329 u32 phystart1_16[16];
330 u32 outbound_hw_event_pid1_16[16];
335 u32 signature;
336 u32 interface_rev;
337 u32 firmware_rev;
338 u32 max_out_io;
339 u32 max_sgl;
340 u32 ctrl_cap_flag;
341 u32 gst_offset;
342 u32 inbound_queue_offset;
343 u32 outbound_queue_offset;
344 u32 inbound_q_nppd_hppd;
345 u32 outbound_hw_event_pid0_3;
346 u32 outbound_hw_event_pid4_7;
347 u32 outbound_ncq_event_pid0_3;
348 u32 outbound_ncq_event_pid4_7;
349 u32 outbound_tgt_ITNexus_event_pid0_3;
350 u32 outbound_tgt_ITNexus_event_pid4_7;
351 u32 outbound_tgt_ssp_event_pid0_3;
352 u32 outbound_tgt_ssp_event_pid4_7;
353 u32 outbound_tgt_smp_event_pid0_3;
354 u32 outbound_tgt_smp_event_pid4_7;
355 u32 upper_event_log_addr;
356 u32 lower_event_log_addr;
357 u32 event_log_size;
358 u32 event_log_option;
359 u32 upper_iop_event_log_addr;
360 u32 lower_iop_event_log_addr;
361 u32 iop_event_log_size;
362 u32 iop_event_log_option;
363 u32 fatal_err_interrupt;
364 u32 fatal_err_dump_offset0;
365 u32 fatal_err_dump_length0;
366 u32 fatal_err_dump_offset1;
367 u32 fatal_err_dump_length1;
368 u32 hda_mode_flag;
369 u32 anolog_setup_table_offset;
370 u32 rsvd[4];
374 u32 signature;
375 u32 interface_rev;
376 u32 firmware_rev;
377 u32 max_out_io;
378 u32 max_sgl;
379 u32 ctrl_cap_flag;
380 u32 gst_offset;
381 u32 inbound_queue_offset;
382 u32 outbound_queue_offset;
383 u32 inbound_q_nppd_hppd;
384 u32 rsvd[8];
385 u32 crc_core_dump;
386 u32 rsvd1;
387 u32 upper_event_log_addr;
388 u32 lower_event_log_addr;
389 u32 event_log_size;
390 u32 event_log_severity;
391 u32 upper_pcs_event_log_addr;
392 u32 lower_pcs_event_log_addr;
393 u32 pcs_event_log_size;
394 u32 pcs_event_log_severity;
395 u32 fatal_err_interrupt;
396 u32 fatal_err_dump_offset0;
397 u32 fatal_err_dump_length0;
398 u32 fatal_err_dump_offset1;
399 u32 fatal_err_dump_length1;
400 u32 gpio_led_mapping;
401 u32 analog_setup_table_offset;
402 u32 int_vec_table_offset;
403 u32 phy_attr_table_offset;
404 u32 port_recovery_timer;
405 u32 interrupt_reassertion_delay;
406 u32 fatal_n_non_fatal_dump; /* 0x28 */
412 u32 gst_len_mpistate;
413 u32 iq_freeze_state0;
414 u32 iq_freeze_state1;
415 u32 msgu_tcnt;
416 u32 iop_tcnt;
417 u32 rsvd;
418 u32 phy_state[8];
419 u32 gpio_input_val;
420 u32 rsvd1[2];
421 u32 recover_err_info[8];
424 u32 gst_len_mpistate;
425 u32 iq_freeze_state0;
426 u32 iq_freeze_state1;
427 u32 msgu_tcnt;
428 u32 iop_tcnt;
429 u32 rsvd[9];
430 u32 gpio_input_val;
431 u32 rsvd1[2];
432 u32 recover_err_info[8];
436 u32 element_pri_size_cnt;
437 u32 upper_base_addr;
438 u32 lower_base_addr;
439 u32 ci_upper_base_addr;
440 u32 ci_lower_base_addr;
441 u32 pi_pci_bar;
442 u32 pi_offset;
443 u32 total_length;
446 u32 reserved;
448 u32 producer_idx;
451 u32 element_size_cnt;
452 u32 upper_base_addr;
453 u32 lower_base_addr;
455 u32 pi_upper_base_addr;
456 u32 pi_lower_base_addr;
457 u32 ci_pci_bar;
458 u32 ci_offset;
459 u32 total_length;
461 u32 interrup_vec_cnt_delay;
462 u32 dinterrup_to_pci_offset;
464 u32 consumer_idx;
469 u32 memsize;
473 u32 irq_id;
487 u32 fatal_bar_loc;
488 u32 forensic_last_offset;
489 u32 fatal_forensic_shift_offset;
490 u32 forensic_fatal_step;
491 u32 evtlog_ib_offset;
492 u32 evtlog_ob_offset;
511 u32 chip_id;
518 u32 id;
519 u32 irq;
520 u32 iomb_size; /* SPC and SPCV IOMB size */
531 u32 logging_level;
532 u32 fw_status;
533 u32 smp_exp_mode;
586 u32 cur_image_offset;
587 u32 cur_image_len;
588 u32 total_image_len;
593 u32 retcode;/*ret code (status)*/
594 u32 phase;/*ret code phase*/
595 u32 phaseCmplt;/*percent complete for the current
597 u32 version;/*Hex encoded firmware version number*/
598 u32 offset;/*Used for downloading firmware */
599 u32 len; /*len of buffer*/
600 u32 size;/* Used in OS VPD and Trace get size
602 u32 reserved;/* padding required for 64 bit
614 u32 len; /* len of buffer */
627 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
629 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
631 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
652 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
653 u32 mem_size, u32 align);
658 u32 opCode, void *payload, u32 responseQueue);
661 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
663 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
667 struct pm8001_device *pm8001_dev, u32 state);
671 void *fw_flash_updata_info, u32 tag);
679 u8 flag, u32 task_tag, u32 cmd_tag);
680 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
705 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
707 u32 device_id);
710 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
712 u32 length, u8 *buf);
714 u32 phy, u32 length, u32 *buf);
715 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
718 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
725 u32 ccb_idx) in pm8001_ccb_task_free_done()