384 	u32 regVal;  in pm8001_bar4_shift()  local
393 		regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);  in pm8001_bar4_shift()
394 	} while ((regVal != shiftValue) && time_before(jiffies, start));  in pm8001_bar4_shift()
396 	if (regVal != shiftValue) {  in pm8001_bar4_shift()
399 			" = 0x%x\n", regVal));  in pm8001_bar4_shift()
758 	u32 regVal, regVal1, regVal2;  in soft_reset_ready_check()  local
765 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)  in soft_reset_ready_check()
767 	if (regVal == SCRATCH_PAD2_FWRDY_RST) {  in soft_reset_ready_check()
786 		regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &  in soft_reset_ready_check()
788 		if (regVal != SCRATCH_PAD2_FWRDY_RST) {  in soft_reset_ready_check()
817 	u32	regVal, toggleVal;  in pm8001_chip_soft_rst()  local
840 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);  in pm8001_chip_soft_rst()
842 		pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));  in pm8001_chip_soft_rst()
852 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);  in pm8001_chip_soft_rst()
854 		pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));  in pm8001_chip_soft_rst()
857 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);  in pm8001_chip_soft_rst()
859 		pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
862 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);  in pm8001_chip_soft_rst()
864 		pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
865 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);  in pm8001_chip_soft_rst()
867 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);  in pm8001_chip_soft_rst()
869 		pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
872 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);  in pm8001_chip_soft_rst()
874 		pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
875 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);  in pm8001_chip_soft_rst()
878 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)  in pm8001_chip_soft_rst()
880 	toggleVal = regVal ^ SCRATCH_PAD1_RST;  in pm8001_chip_soft_rst()
901 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);  in pm8001_chip_soft_rst()
910 	regVal &= ~(0x00003b00);  in pm8001_chip_soft_rst()
912 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);  in pm8001_chip_soft_rst()
962 	regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);  in pm8001_chip_soft_rst()
965 				" = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
967 	regVal &= 0xFFFFFFFC;  in pm8001_chip_soft_rst()
968 	pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);  in pm8001_chip_soft_rst()
979 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
982 		":= 0x%x\n", regVal));  in pm8001_chip_soft_rst()
983 	regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);  in pm8001_chip_soft_rst()
984 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
987 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
990 		": = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
991 	regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);  in pm8001_chip_soft_rst()
992 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
998 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
1001 		":= 0x%x\n", regVal));  in pm8001_chip_soft_rst()
1002 	regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);  in pm8001_chip_soft_rst()
1003 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
1020 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);  in pm8001_chip_soft_rst()
1029 	regVal |= (GSM_CONFIG_RESET_VALUE);  in pm8001_chip_soft_rst()
1030 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);  in pm8001_chip_soft_rst()
1037 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);  in pm8001_chip_soft_rst()
1041 		" = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
1048 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);  in pm8001_chip_soft_rst()
1055 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);  in pm8001_chip_soft_rst()
1071 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
1072 	regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);  in pm8001_chip_soft_rst()
1073 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
1084 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &  in pm8001_chip_soft_rst()
1086 		} while ((regVal != toggleVal) && (--max_wait_count));  in pm8001_chip_soft_rst()
1089 			regVal = pm8001_cr32(pm8001_ha, 0,  in pm8001_chip_soft_rst()
1094 				toggleVal, regVal));  in pm8001_chip_soft_rst()
1119 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in pm8001_chip_soft_rst()
1123 				" = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
1124 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);  in pm8001_chip_soft_rst()
1128 				" = 0x%x\n", regVal));  in pm8001_chip_soft_rst()
1152 	u32 regVal;  in pm8001_hw_chip_rst()  local
1157 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);  in pm8001_hw_chip_rst()
1158 	regVal &= ~(SPC_REG_RESET_DEVICE);  in pm8001_hw_chip_rst()
1159 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);  in pm8001_hw_chip_rst()
1165 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);  in pm8001_hw_chip_rst()
1166 	regVal |= SPC_REG_RESET_DEVICE;  in pm8001_hw_chip_rst()
1167 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);  in pm8001_hw_chip_rst()