217 chip_init(int io_port)  in chip_init()  argument
219 	REG1(io_port);  in chip_init()
220 	outb(0x01, io_port + PIO_STATUS);  in chip_init()
221 	outb(0x00, io_port + PIO_FLAG);  in chip_init()
223 	outb(C4_IMG, io_port + CONFIG4);	/* REG0(io_port); */  in chip_init()
224 	outb(C3_IMG, io_port + CONFIG3);  in chip_init()
225 	outb(C2_IMG, io_port + CONFIG2);  in chip_init()
226 	outb(C1_IMG, io_port + CONFIG1);  in chip_init()
228 	outb(0x05, io_port + CLKCONV);	/* clock conversion factor */  in chip_init()
229 	outb(0x9C, io_port + SRTIMOUT);	/* Selection timeout */  in chip_init()
230 	outb(0x05, io_port + SYNCPRD);	/* Synchronous transfer period */  in chip_init()
231 	outb(SYNC_MODE, io_port + SYNCOFF);	/* synchronous mode */    in chip_init()
235 SYM53C500_int_host_reset(int io_port)  in SYM53C500_int_host_reset()  argument
237 	outb(C4_IMG, io_port + CONFIG4);	/* REG0(io_port); */  in SYM53C500_int_host_reset()
238 	outb(CHIP_RESET, io_port + CMD_REG);  in SYM53C500_int_host_reset()
239 	outb(SCSI_NOP, io_port + CMD_REG);	/* required after reset */  in SYM53C500_int_host_reset()
240 	outb(SCSI_RESET, io_port + CMD_REG);  in SYM53C500_int_host_reset()
241 	chip_init(io_port);  in SYM53C500_int_host_reset()
359 	int port_base = dev->io_port;  in SYM53C500_intr()
527 	if (shost->io_port && shost->n_io_port)  in SYM53C500_release()
528 		release_region(shost->io_port, shost->n_io_port);  in SYM53C500_release()
545 	    SChost->io_port, SChost->irq, data->fast_pio ? "fast" : "slow");  in SYM53C500_info()
553 	int port_base = SCpnt->device->host->io_port;  in SYM53C500_queue_lck()
591 	int port_base = SCpnt->device->host->io_port;  in DEF_SCSI_QCMD()
780 	host->io_port = port_base;  in SYM53C500_config()