305 #define NSP32_DEBUG_INTR		BIT(3)  macro
440 	nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
443 		nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1178 	nsp32_dbg(NSP32_DEBUG_INTR,   in do_nsp32_isr()
1182 		nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);  in do_nsp32_isr()
1204 		nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");  in do_nsp32_isr()
1239 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1264 			nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");  in do_nsp32_isr()
1276 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1280 			nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",   in do_nsp32_isr()
1282 			nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",   in do_nsp32_isr()
1284 			nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",   in do_nsp32_isr()
1286 			nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",   in do_nsp32_isr()
1345 			nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");  in do_nsp32_isr()
1357 		nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");  in do_nsp32_isr()
1361 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");  in do_nsp32_isr()
1368 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");  in do_nsp32_isr()
1375 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");  in do_nsp32_isr()
1381 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");  in do_nsp32_isr()
1382 			nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);  in do_nsp32_isr()
1392 		nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");  in do_nsp32_isr()
1396 			nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");  in do_nsp32_isr()
1411 		nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");  in do_nsp32_isr()
1426 	nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1438 	nsp32_dbg(NSP32_DEBUG_INTR, "exit");  in do_nsp32_isr()