Lines Matching refs:tmp
54 u32 tmp, setting_0 = 0, setting_1 = 0; in set_phy_tuning() local
97 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
98 tmp &= ~(0xFBE << 16); in set_phy_tuning()
99 tmp |= (((phy_tuning.trans_emp_en << 11) | in set_phy_tuning()
102 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
106 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
107 tmp &= ~(0xC000); in set_phy_tuning()
108 tmp |= (phy_tuning.trans_amp_adj << 14); in set_phy_tuning()
109 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
116 u32 tmp; in set_phy_ffe_tuning() local
131 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
132 tmp &= ~0xFF; in set_phy_ffe_tuning()
135 tmp |= ((0x1 << 7) | in set_phy_ffe_tuning()
139 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
146 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
147 tmp &= ~0x40001; in set_phy_ffe_tuning()
150 tmp |= (0 << 18); in set_phy_ffe_tuning()
151 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
159 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
160 tmp &= ~0xFFF; in set_phy_ffe_tuning()
163 tmp |= ((0x3F << 6) | (0x0 << 0)); in set_phy_ffe_tuning()
164 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
171 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
172 tmp &= ~0x8; in set_phy_ffe_tuning()
175 tmp |= (0 << 3); in set_phy_ffe_tuning()
176 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
263 u32 tmp; in mvs_94xx_enable_xmt() local
265 tmp = mr32(MVS_PCS); in mvs_94xx_enable_xmt()
266 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_94xx_enable_xmt()
267 mw32(MVS_PCS, tmp); in mvs_94xx_enable_xmt()
272 u32 tmp; in mvs_94xx_phy_reset() local
276 tmp = mvs_read_port_cfg_data(mvi, phy_id); in mvs_94xx_phy_reset()
277 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); in mvs_94xx_phy_reset()
278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); in mvs_94xx_phy_reset()
281 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_94xx_phy_reset()
282 tmp &= ~PHYEV_RDY_CH; in mvs_94xx_phy_reset()
283 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
285 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
286 tmp |= PHY_RST_HARD; in mvs_94xx_phy_reset()
287 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
289 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
292 } while ((tmp & PHY_RST_HARD) && delay); in mvs_94xx_phy_reset()
296 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
297 tmp |= PHY_RST; in mvs_94xx_phy_reset()
298 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
304 u32 tmp; in mvs_94xx_phy_disable() local
306 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_disable()
307 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); in mvs_94xx_phy_disable()
312 u32 tmp; in mvs_94xx_phy_enable() local
328 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_enable()
329 tmp |= bit(0); in mvs_94xx_phy_enable()
330 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); in mvs_94xx_phy_enable()
337 u32 tmp, cctl; in mvs_94xx_init() local
343 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
344 tmp &= ~PCTL_PWR_OFF; in mvs_94xx_init()
345 tmp |= PCTL_PHY_DSBL; in mvs_94xx_init()
346 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
358 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
359 tmp &= ~PCTL_PWR_OFF; in mvs_94xx_init()
360 tmp |= PCTL_COM_ON; in mvs_94xx_init()
361 tmp &= ~PCTL_PHY_DSBL; in mvs_94xx_init()
362 tmp |= PCTL_LINK_RST; in mvs_94xx_init()
363 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
365 tmp &= ~PCTL_LINK_RST; in mvs_94xx_init()
366 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
401 tmp = mvs_cr32(mvi, CMD_SAS_CTL1); in mvs_94xx_init()
405 tmp &= ~0xffff; in mvs_94xx_init()
406 tmp |= 0x007f; in mvs_94xx_init()
407 mvs_cw32(mvi, CMD_SAS_CTL1, tmp); in mvs_94xx_init()
412 tmp = mr32(MVS_PA_VSR_PORT); in mvs_94xx_init()
413 tmp &= 0xFFFF00FF; in mvs_94xx_init()
414 tmp |= 0x00003300; in mvs_94xx_init()
415 mw32(MVS_PA_VSR_PORT, tmp); in mvs_94xx_init()
459 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_94xx_init()
460 tmp &= ~PHYEV_SIG_FIS; in mvs_94xx_init()
461 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_94xx_init()
464 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | in mvs_94xx_init()
466 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_94xx_init()
480 tmp = mr32(MVS_PCS); in mvs_94xx_init()
481 tmp |= PCS_CMD_RST; in mvs_94xx_init()
482 tmp &= ~PCS_SELF_CLEAR; in mvs_94xx_init()
483 mw32(MVS_PCS, tmp); in mvs_94xx_init()
488 tmp = 0; in mvs_94xx_init()
495 tmp = 0x10000 | interrupt_coalescing; in mvs_94xx_init()
496 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_94xx_init()
507 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | in mvs_94xx_init()
509 tmp |= CINT_PHY_MASK; in mvs_94xx_init()
510 mw32(MVS_INT_MASK, tmp); in mvs_94xx_init()
512 tmp = mvs_cr32(mvi, CMD_LINK_TIMER); in mvs_94xx_init()
513 tmp |= 0xFFFF0000; in mvs_94xx_init()
514 mvs_cw32(mvi, CMD_LINK_TIMER, tmp); in mvs_94xx_init()
517 tmp = 0x003F003F; in mvs_94xx_init()
518 mvs_cw32(mvi, CMD_PL_TIMER, tmp); in mvs_94xx_init()
521 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1); in mvs_94xx_init()
522 tmp |= 0xFFFF007F; in mvs_94xx_init()
523 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp); in mvs_94xx_init()
527 tmp = mvs_cr32(mvi, CMD_SL_MODE0); in mvs_94xx_init()
528 tmp |= 0x00000300; in mvs_94xx_init()
530 tmp &= 0xFFFFFFFE; in mvs_94xx_init()
531 mvs_cw32(mvi, CMD_SL_MODE0, tmp); in mvs_94xx_init()
564 u32 tmp; in mvs_94xx_interrupt_enable() local
566 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_enable()
567 tmp |= (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); in mvs_94xx_interrupt_enable()
568 mw32(MVS_GBL_INT_STAT, tmp); in mvs_94xx_interrupt_enable()
569 writel(tmp, regs + 0x0C); in mvs_94xx_interrupt_enable()
570 writel(tmp, regs + 0x10); in mvs_94xx_interrupt_enable()
571 writel(tmp, regs + 0x14); in mvs_94xx_interrupt_enable()
572 writel(tmp, regs + 0x18); in mvs_94xx_interrupt_enable()
573 mw32(MVS_GBL_CTL, tmp); in mvs_94xx_interrupt_enable()
579 u32 tmp; in mvs_94xx_interrupt_disable() local
581 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_disable()
583 tmp &= ~(MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); in mvs_94xx_interrupt_disable()
584 mw32(MVS_GBL_INT_STAT, tmp); in mvs_94xx_interrupt_disable()
585 writel(tmp, regs + 0x0C); in mvs_94xx_interrupt_disable()
586 writel(tmp, regs + 0x10); in mvs_94xx_interrupt_disable()
587 writel(tmp, regs + 0x14); in mvs_94xx_interrupt_disable()
588 writel(tmp, regs + 0x18); in mvs_94xx_interrupt_disable()
589 mw32(MVS_GBL_CTL, tmp); in mvs_94xx_interrupt_disable()
622 u32 tmp; in mvs_94xx_command_active() local
623 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); in mvs_94xx_command_active()
624 if (tmp && 1 << (slot_idx % 32)) { in mvs_94xx_command_active()
625 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx); in mvs_94xx_command_active()
629 tmp = mvs_cr32(mvi, in mvs_94xx_command_active()
631 } while (tmp & 1 << (slot_idx % 32)); in mvs_94xx_command_active()
638 u32 tmp; in mvs_94xx_clear_srs_irq() local
641 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
642 if (tmp) { in mvs_94xx_clear_srs_irq()
643 mv_dprintk("check SRS 0 %08X.\n", tmp); in mvs_94xx_clear_srs_irq()
644 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_94xx_clear_srs_irq()
646 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
647 if (tmp) { in mvs_94xx_clear_srs_irq()
648 mv_dprintk("check SRS 1 %08X.\n", tmp); in mvs_94xx_clear_srs_irq()
649 mw32(MVS_INT_STAT_SRS_1, tmp); in mvs_94xx_clear_srs_irq()
653 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
655 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
657 if (tmp & (1 << (reg_set % 32))) { in mvs_94xx_clear_srs_irq()
671 u32 tmp; in mvs_94xx_issue_stop() local
674 tmp = mr32(MVS_INT_STAT); in mvs_94xx_issue_stop()
675 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP); in mvs_94xx_issue_stop()
676 tmp = mr32(MVS_PCS) | 0xFF00; in mvs_94xx_issue_stop()
677 mw32(MVS_PCS, tmp); in mvs_94xx_issue_stop()
866 u32 tmp; in mvs_94xx_phy_set_link_rate() local
868 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_set_link_rate()
872 tmp &= ~(0x3 << 12); in mvs_94xx_phy_set_link_rate()
873 tmp |= lrmax; in mvs_94xx_phy_set_link_rate()
875 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_set_link_rate()
881 u32 tmp; in mvs_94xx_clear_active_cmds() local
883 tmp = mr32(MVS_STP_REG_SET_0); in mvs_94xx_clear_active_cmds()
885 mw32(MVS_STP_REG_SET_0, tmp); in mvs_94xx_clear_active_cmds()
886 tmp = mr32(MVS_STP_REG_SET_1); in mvs_94xx_clear_active_cmds()
888 mw32(MVS_STP_REG_SET_1, tmp); in mvs_94xx_clear_active_cmds()
988 u32 tmp = 0; in mvs_94xx_tune_interrupt() local
1002 tmp = 0x10000 | time; in mvs_94xx_tune_interrupt()
1003 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_94xx_tune_interrupt()