Lines Matching refs:phy_id
51 void set_phy_tuning(struct mvs_info *mvi, int phy_id, in set_phy_tuning() argument
96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0); in set_phy_tuning()
97 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
102 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1); in set_phy_tuning()
106 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
109 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, in set_phy_ffe_tuning() argument
130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); in set_phy_ffe_tuning()
131 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
139 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
146 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
151 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); in set_phy_ffe_tuning()
159 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
164 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
171 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
176 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) in set_phy_rate() argument
183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in set_phy_rate()
184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_rate()
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); in set_phy_rate()
219 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) in mvs_94xx_config_reg_from_hba() argument
222 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
224 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; in mvs_94xx_config_reg_from_hba()
225 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; in mvs_94xx_config_reg_from_hba()
226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; in mvs_94xx_config_reg_from_hba()
229 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
234 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; in mvs_94xx_config_reg_from_hba()
241 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; in mvs_94xx_config_reg_from_hba()
247 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
250 mvi->hba_info_param.phy_rate[phy_id] = 0x2; in mvs_94xx_config_reg_from_hba()
252 set_phy_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
253 mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
254 set_phy_ffe_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
255 mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
256 set_phy_rate(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
257 mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
260 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) in mvs_94xx_enable_xmt() argument
266 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_94xx_enable_xmt()
270 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) in mvs_94xx_phy_reset() argument
275 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL); in mvs_94xx_phy_reset()
276 tmp = mvs_read_port_cfg_data(mvi, phy_id); in mvs_94xx_phy_reset()
277 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); in mvs_94xx_phy_reset()
278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); in mvs_94xx_phy_reset()
281 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_94xx_phy_reset()
283 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
285 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
287 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
289 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
296 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
298 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
302 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_disable() argument
305 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_disable()
306 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_disable()
307 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); in mvs_94xx_phy_disable()
310 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_enable() argument
317 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
318 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); in mvs_94xx_phy_enable()
321 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); in mvs_94xx_phy_enable()
322 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); in mvs_94xx_phy_enable()
323 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
324 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); in mvs_94xx_phy_enable()
327 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_enable()
328 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_enable()
330 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); in mvs_94xx_phy_enable()
823 att_dev_info |= (u32)id->phy_id<<24; in mvs_94xx_make_dev_info()
862 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, in mvs_94xx_phy_set_link_rate() argument
868 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_set_link_rate()
875 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_set_link_rate()
876 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD); in mvs_94xx_phy_set_link_rate()