Lines Matching refs:phy_cfg
182 union reg_phy_cfg phy_cfg, phy_cfg_tmp; in set_phy_rate() local
185 phy_cfg.v = 0; in set_phy_rate()
186 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy; in set_phy_rate()
187 phy_cfg.u.sas_support = 1; in set_phy_rate()
188 phy_cfg.u.sata_support = 1; in set_phy_rate()
189 phy_cfg.u.sata_host_mode = 1; in set_phy_rate()
194 phy_cfg.u.speed_support = 1; in set_phy_rate()
195 phy_cfg.u.snw_3_support = 0; in set_phy_rate()
196 phy_cfg.u.tx_lnk_parity = 1; in set_phy_rate()
197 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30; in set_phy_rate()
202 phy_cfg.u.speed_support = 3; in set_phy_rate()
203 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c; in set_phy_rate()
204 phy_cfg.u.tx_lgcl_lnk_rate = 0x08; in set_phy_rate()
209 phy_cfg.u.speed_support = 7; in set_phy_rate()
210 phy_cfg.u.snw_3_support = 1; in set_phy_rate()
211 phy_cfg.u.tx_lnk_parity = 1; in set_phy_rate()
212 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f; in set_phy_rate()
213 phy_cfg.u.tx_lgcl_lnk_rate = 0x09; in set_phy_rate()
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); in set_phy_rate()