267 	mw32(MVS_PCS, tmp);  in mvs_94xx_enable_xmt()
346 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
363 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
366 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
371 	mw32(MVS_PORTS_IMP, 0xFF);  in mvs_94xx_init()
374 		mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);  in mvs_94xx_init()
375 		mw32(MVS_PA_VSR_PORT, 0x00018080);  in mvs_94xx_init()
377 	mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);  in mvs_94xx_init()
380 		mw32(MVS_PA_VSR_PORT, 0x0084d4fe);  in mvs_94xx_init()
383 		mw32(MVS_PA_VSR_PORT, 0x0084fffe);  in mvs_94xx_init()
386 		mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);  in mvs_94xx_init()
387 		mw32(MVS_PA_VSR_PORT, 0x08001006);  in mvs_94xx_init()
388 		mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);  in mvs_94xx_init()
389 		mw32(MVS_PA_VSR_PORT, 0x0000705f);  in mvs_94xx_init()
393 	mw32(MVS_PCS, 0);		/* MVS_PCS */  in mvs_94xx_init()
394 	mw32(MVS_STP_REG_SET_0, 0);  in mvs_94xx_init()
395 	mw32(MVS_STP_REG_SET_1, 0);  in mvs_94xx_init()
411 	mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);  in mvs_94xx_init()
415 	mw32(MVS_PA_VSR_PORT, tmp);  in mvs_94xx_init()
417 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);  in mvs_94xx_init()
418 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);  in mvs_94xx_init()
420 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);  in mvs_94xx_init()
421 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);  in mvs_94xx_init()
423 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);  in mvs_94xx_init()
424 	mw32(MVS_TX_LO, mvi->tx_dma);  in mvs_94xx_init()
425 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);  in mvs_94xx_init()
427 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ);  in mvs_94xx_init()
428 	mw32(MVS_RX_LO, mvi->rx_dma);  in mvs_94xx_init()
429 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);  in mvs_94xx_init()
483 	mw32(MVS_PCS, tmp);  in mvs_94xx_init()
490 		mw32(MVS_INT_COAL, 0x1ff | COAL_EN);  in mvs_94xx_init()
492 		mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);  in mvs_94xx_init()
496 	mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_94xx_init()
499 	mw32(MVS_TX_CFG, 0);  in mvs_94xx_init()
500 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);  in mvs_94xx_init()
501 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);  in mvs_94xx_init()
503 	mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |  in mvs_94xx_init()
510 	mw32(MVS_INT_MASK, tmp);  in mvs_94xx_init()
534 	mw32(MVS_INT_MASK_SRS_0, 0xFFFF);  in mvs_94xx_init()
568 	mw32(MVS_GBL_INT_STAT, tmp);  in mvs_94xx_interrupt_enable()
573 	mw32(MVS_GBL_CTL, tmp);  in mvs_94xx_interrupt_enable()
584 	mw32(MVS_GBL_INT_STAT, tmp);  in mvs_94xx_interrupt_disable()
589 	mw32(MVS_GBL_CTL, tmp);  in mvs_94xx_interrupt_disable()
644 			mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_94xx_clear_srs_irq()
649 			mw32(MVS_INT_STAT_SRS_1, tmp);  in mvs_94xx_clear_srs_irq()
660 				mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));  in mvs_94xx_clear_srs_irq()
662 				mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));  in mvs_94xx_clear_srs_irq()
675 	mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);  in mvs_94xx_issue_stop()
677 	mw32(MVS_PCS, tmp);  in mvs_94xx_issue_stop()
705 	mw32(MVS_NON_NCQ_ERR_0, err_0);  in mvs_94xx_non_spec_ncq_error()
706 	mw32(MVS_NON_NCQ_ERR_1, err_1);  in mvs_94xx_non_spec_ncq_error()
884 	mw32(MVS_STP_REG_SET_0, 0);  in mvs_94xx_clear_active_cmds()
885 	mw32(MVS_STP_REG_SET_0, tmp);  in mvs_94xx_clear_active_cmds()
887 	mw32(MVS_STP_REG_SET_1, 0);  in mvs_94xx_clear_active_cmds()
888 	mw32(MVS_STP_REG_SET_1, tmp);  in mvs_94xx_clear_active_cmds()
901 	 mw32(SPI_RD_DATA_REG_94XX, data);  in mvs_94xx_spi_write_data()
921 		mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));  in mvs_94xx_spi_buildcmd()
933 	mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);  in mvs_94xx_spi_issuecmd()
994 		mw32(MVS_INT_COAL, 0);  in mvs_94xx_tune_interrupt()
995 		mw32(MVS_INT_COAL_TMOUT, 0x10000);  in mvs_94xx_tune_interrupt()
998 			mw32(MVS_INT_COAL, 0x1ff|COAL_EN);  in mvs_94xx_tune_interrupt()
1000 			mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);  in mvs_94xx_tune_interrupt()
1003 		mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_94xx_tune_interrupt()