Lines Matching refs:mvi
30 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i) in mvs_94xx_detect_porttype() argument
33 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_detect_porttype()
36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3); in mvs_94xx_detect_porttype()
37 reg = mvs_read_port_vsr_data(mvi, i); in mvs_94xx_detect_porttype()
51 void set_phy_tuning(struct mvs_info *mvi, int phy_id, in set_phy_tuning() argument
70 if (mvi->pdev->revision == VANIR_A0_REV) in set_phy_tuning()
96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0); in set_phy_tuning()
97 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
102 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1); in set_phy_tuning()
106 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
109 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id, in set_phy_ffe_tuning() argument
119 if ((mvi->pdev->revision == VANIR_A0_REV) in set_phy_ffe_tuning()
120 || (mvi->pdev->revision == VANIR_B0_REV)) in set_phy_ffe_tuning()
130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL); in set_phy_ffe_tuning()
131 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
139 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
146 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
151 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL); in set_phy_ffe_tuning()
159 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
164 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL); in set_phy_ffe_tuning()
171 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
176 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate) in set_phy_rate() argument
183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in set_phy_rate()
184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_rate()
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v); in set_phy_rate()
219 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id) in mvs_94xx_config_reg_from_hba() argument
222 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
224 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; in mvs_94xx_config_reg_from_hba()
225 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; in mvs_94xx_config_reg_from_hba()
226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; in mvs_94xx_config_reg_from_hba()
229 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
231 switch (mvi->pdev->revision) { in mvs_94xx_config_reg_from_hba()
234 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; in mvs_94xx_config_reg_from_hba()
241 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; in mvs_94xx_config_reg_from_hba()
247 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
250 mvi->hba_info_param.phy_rate[phy_id] = 0x2; in mvs_94xx_config_reg_from_hba()
252 set_phy_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
253 mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
254 set_phy_ffe_tuning(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
255 mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
256 set_phy_rate(mvi, phy_id, in mvs_94xx_config_reg_from_hba()
257 mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
260 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id) in mvs_94xx_enable_xmt() argument
262 void __iomem *regs = mvi->regs; in mvs_94xx_enable_xmt()
270 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) in mvs_94xx_phy_reset() argument
275 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL); in mvs_94xx_phy_reset()
276 tmp = mvs_read_port_cfg_data(mvi, phy_id); in mvs_94xx_phy_reset()
277 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); in mvs_94xx_phy_reset()
278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); in mvs_94xx_phy_reset()
281 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_94xx_phy_reset()
283 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
285 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
287 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
289 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
296 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
298 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
302 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_disable() argument
305 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_disable()
306 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_disable()
307 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); in mvs_94xx_phy_disable()
310 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id) in mvs_94xx_phy_enable() argument
315 revision = mvi->pdev->revision; in mvs_94xx_phy_enable()
317 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
318 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1); in mvs_94xx_phy_enable()
321 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL); in mvs_94xx_phy_enable()
322 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006); in mvs_94xx_phy_enable()
323 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA); in mvs_94xx_phy_enable()
324 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f); in mvs_94xx_phy_enable()
327 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2); in mvs_94xx_phy_enable()
328 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_enable()
330 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); in mvs_94xx_phy_enable()
333 static int mvs_94xx_init(struct mvs_info *mvi) in mvs_94xx_init() argument
335 void __iomem *regs = mvi->regs; in mvs_94xx_init()
340 revision = mvi->pdev->revision; in mvs_94xx_init()
341 mvs_show_pcie_usage(mvi); in mvs_94xx_init()
342 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
357 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
398 mvs_phy_hacks(mvi); in mvs_94xx_init()
401 tmp = mvs_cr32(mvi, CMD_SAS_CTL1); in mvs_94xx_init()
407 mvs_cw32(mvi, CMD_SAS_CTL1, tmp); in mvs_94xx_init()
417 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); in mvs_94xx_init()
418 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); in mvs_94xx_init()
420 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); in mvs_94xx_init()
421 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); in mvs_94xx_init()
424 mw32(MVS_TX_LO, mvi->tx_dma); in mvs_94xx_init()
425 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); in mvs_94xx_init()
428 mw32(MVS_RX_LO, mvi->rx_dma); in mvs_94xx_init()
429 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); in mvs_94xx_init()
431 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_94xx_init()
432 mvs_94xx_phy_disable(mvi, i); in mvs_94xx_init()
434 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4, in mvs_94xx_init()
435 cpu_to_le64(mvi->phy[i].dev_sas_addr)); in mvs_94xx_init()
437 mvs_94xx_enable_xmt(mvi, i); in mvs_94xx_init()
438 mvs_94xx_config_reg_from_hba(mvi, i); in mvs_94xx_init()
439 mvs_94xx_phy_enable(mvi, i); in mvs_94xx_init()
441 mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD); in mvs_94xx_init()
443 mvs_94xx_detect_porttype(mvi, i); in mvs_94xx_init()
446 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
457 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_94xx_init()
459 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_94xx_init()
461 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_94xx_init()
466 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_94xx_init()
469 mvs_update_phyinfo(mvi, i, 1); in mvs_94xx_init()
512 tmp = mvs_cr32(mvi, CMD_LINK_TIMER); in mvs_94xx_init()
514 mvs_cw32(mvi, CMD_LINK_TIMER, tmp); in mvs_94xx_init()
518 mvs_cw32(mvi, CMD_PL_TIMER, tmp); in mvs_94xx_init()
521 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1); in mvs_94xx_init()
523 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp); in mvs_94xx_init()
527 tmp = mvs_cr32(mvi, CMD_SL_MODE0); in mvs_94xx_init()
531 mvs_cw32(mvi, CMD_SL_MODE0, tmp); in mvs_94xx_init()
539 static int mvs_94xx_ioremap(struct mvs_info *mvi) in mvs_94xx_ioremap() argument
541 if (!mvs_ioremap(mvi, 2, -1)) { in mvs_94xx_ioremap()
542 mvi->regs_ex = mvi->regs + 0x10200; in mvs_94xx_ioremap()
543 mvi->regs += 0x20000; in mvs_94xx_ioremap()
544 if (mvi->id == 1) in mvs_94xx_ioremap()
545 mvi->regs += 0x4000; in mvs_94xx_ioremap()
551 static void mvs_94xx_iounmap(struct mvs_info *mvi) in mvs_94xx_iounmap() argument
553 if (mvi->regs) { in mvs_94xx_iounmap()
554 mvi->regs -= 0x20000; in mvs_94xx_iounmap()
555 if (mvi->id == 1) in mvs_94xx_iounmap()
556 mvi->regs -= 0x4000; in mvs_94xx_iounmap()
557 mvs_iounmap(mvi->regs); in mvs_94xx_iounmap()
561 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi) in mvs_94xx_interrupt_enable() argument
563 void __iomem *regs = mvi->regs_ex; in mvs_94xx_interrupt_enable()
576 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi) in mvs_94xx_interrupt_disable() argument
578 void __iomem *regs = mvi->regs_ex; in mvs_94xx_interrupt_disable()
592 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq) in mvs_94xx_isr_status() argument
594 void __iomem *regs = mvi->regs_ex; in mvs_94xx_isr_status()
596 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_94xx_isr_status()
605 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) in mvs_94xx_isr() argument
607 void __iomem *regs = mvi->regs; in mvs_94xx_isr()
609 if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) || in mvs_94xx_isr()
610 ((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) { in mvs_94xx_isr()
613 spin_lock(&mvi->lock); in mvs_94xx_isr()
614 mvs_int_full(mvi); in mvs_94xx_isr()
615 spin_unlock(&mvi->lock); in mvs_94xx_isr()
620 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx) in mvs_94xx_command_active() argument
623 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); in mvs_94xx_command_active()
626 mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3), in mvs_94xx_command_active()
629 tmp = mvs_cr32(mvi, in mvs_94xx_command_active()
635 void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_94xx_clear_srs_irq() argument
637 void __iomem *regs = mvi->regs; in mvs_94xx_clear_srs_irq()
667 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, in mvs_94xx_issue_stop() argument
670 void __iomem *regs = mvi->regs; in mvs_94xx_issue_stop()
672 mvs_94xx_clear_srs_irq(mvi, 0, 1); in mvs_94xx_issue_stop()
680 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi) in mvs_94xx_non_spec_ncq_error() argument
682 void __iomem *regs = mvi->regs; in mvs_94xx_non_spec_ncq_error()
694 device = mvs_find_dev_by_reg_set(mvi, i); in mvs_94xx_non_spec_ncq_error()
696 mvs_release_task(mvi, device->sas_device); in mvs_94xx_non_spec_ncq_error()
699 device = mvs_find_dev_by_reg_set(mvi, i+32); in mvs_94xx_non_spec_ncq_error()
701 mvs_release_task(mvi, device->sas_device); in mvs_94xx_non_spec_ncq_error()
709 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) in mvs_94xx_free_reg_set() argument
711 void __iomem *regs = mvi->regs; in mvs_94xx_free_reg_set()
717 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
719 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); in mvs_94xx_free_reg_set()
721 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32)); in mvs_94xx_free_reg_set()
728 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) in mvs_94xx_assign_reg_set() argument
731 void __iomem *regs = mvi->regs; in mvs_94xx_assign_reg_set()
736 i = mv_ffc64(mvi->sata_reg_set); in mvs_94xx_assign_reg_set()
738 mvi->sata_reg_set |= bit(i); in mvs_94xx_assign_reg_set()
739 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32)); in mvs_94xx_assign_reg_set()
743 mvi->sata_reg_set |= bit(i); in mvs_94xx_assign_reg_set()
744 w_reg_set_enable(i, (u32)mvi->sata_reg_set); in mvs_94xx_assign_reg_set()
766 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i) in mvs_94xx_oob_done() argument
769 phy_st = mvs_read_phy_ctl(mvi, i); in mvs_94xx_oob_done()
775 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id, in mvs_94xx_get_dev_identify_frame() argument
782 mvs_write_port_cfg_addr(mvi, port_id, in mvs_94xx_get_dev_identify_frame()
784 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); in mvs_94xx_get_dev_identify_frame()
789 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id, in mvs_94xx_get_att_identify_frame() argument
796 mvs_write_port_cfg_addr(mvi, port_id, in mvs_94xx_get_att_identify_frame()
798 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id)); in mvs_94xx_get_att_identify_frame()
800 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]); in mvs_94xx_get_att_identify_frame()
832 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i, in mvs_94xx_fix_phy_info() argument
835 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_fix_phy_info()
845 mvs_94xx_get_dev_identify_frame(mvi, i, id); in mvs_94xx_fix_phy_info()
849 mvs_94xx_get_att_identify_frame(mvi, i, id); in mvs_94xx_fix_phy_info()
857 mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT); in mvs_94xx_fix_phy_info()
858 mvs_write_port_cfg_data(mvi, i, 0x04); in mvs_94xx_fix_phy_info()
862 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, in mvs_94xx_phy_set_link_rate() argument
868 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_set_link_rate()
875 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_set_link_rate()
876 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD); in mvs_94xx_phy_set_link_rate()
879 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi) in mvs_94xx_clear_active_cmds() argument
882 void __iomem *regs = mvi->regs; in mvs_94xx_clear_active_cmds()
892 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi) in mvs_94xx_spi_read_data() argument
894 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_read_data()
898 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data) in mvs_94xx_spi_write_data() argument
900 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_write_data()
905 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi, in mvs_94xx_spi_buildcmd() argument
913 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_buildcmd()
930 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) in mvs_94xx_spi_issuecmd() argument
932 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_issuecmd()
938 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) in mvs_94xx_spi_waitdataready() argument
940 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_waitdataready()
953 void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, in mvs_94xx_fix_dma() argument
965 if ((mvi->pdev->revision == VANIR_A0_REV) || in mvs_94xx_fix_dma()
966 (mvi->pdev->revision == VANIR_B0_REV)) in mvs_94xx_fix_dma()
968 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1; in mvs_94xx_fix_dma()
985 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time) in mvs_94xx_tune_interrupt() argument
987 void __iomem *regs = mvi->regs; in mvs_94xx_tune_interrupt()