Lines Matching refs:tmp
47 u32 tmp; in mvs_64xx_enable_xmt() local
49 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
54 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
86 u32 reg, tmp; in mvs_64xx_stp_reset() local
97 tmp = reg; in mvs_64xx_stp_reset()
99 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
101 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
105 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
109 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_stp_reset()
114 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_stp_reset()
122 u32 tmp; in mvs_64xx_phy_reset() local
123 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_64xx_phy_reset()
124 tmp &= ~PHYEV_RDY_CH; in mvs_64xx_phy_reset()
125 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
126 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
128 tmp |= PHY_RST_HARD; in mvs_64xx_phy_reset()
130 tmp |= PHY_RST; in mvs_64xx_phy_reset()
131 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
134 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
135 } while (tmp & PHY_RST_HARD); in mvs_64xx_phy_reset()
142 u32 tmp; in mvs_64xx_clear_srs_irq() local
144 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()
145 if (tmp) { in mvs_64xx_clear_srs_irq()
146 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); in mvs_64xx_clear_srs_irq()
147 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_clear_srs_irq()
150 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()
151 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
162 u32 tmp; in mvs_64xx_chip_reset() local
167 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
170 if (!(tmp & HBA_RST)) { in mvs_64xx_chip_reset()
172 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_chip_reset()
173 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_chip_reset()
174 tmp |= PCTL_PHY_DSBL; in mvs_64xx_chip_reset()
175 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_chip_reset()
177 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_chip_reset()
178 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_chip_reset()
179 tmp |= PCTL_PHY_DSBL; in mvs_64xx_chip_reset()
180 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_chip_reset()
186 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
189 if (!(tmp & HBA_RST)) { in mvs_64xx_chip_reset()
212 u32 tmp; in mvs_64xx_phy_disable() local
221 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_disable()
222 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); in mvs_64xx_phy_disable()
223 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_disable()
225 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_phy_disable()
226 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); in mvs_64xx_phy_disable()
227 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_disable()
234 u32 tmp; in mvs_64xx_phy_enable() local
243 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_enable()
244 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); in mvs_64xx_phy_enable()
245 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_enable()
247 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_phy_enable()
248 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); in mvs_64xx_phy_enable()
249 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_enable()
257 u32 tmp, cctl; in mvs_64xx_init() local
263 tmp = mvs_64xx_chip_reset(mvi); in mvs_64xx_init()
264 if (tmp) in mvs_64xx_init()
265 return tmp; in mvs_64xx_init()
267 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_init()
268 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
269 tmp |= PCTL_PHY_DSBL; in mvs_64xx_init()
270 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
283 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); in mvs_64xx_init()
284 tmp &= ~PRD_REQ_MASK; in mvs_64xx_init()
285 tmp |= PRD_REQ_SIZE; in mvs_64xx_init()
286 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); in mvs_64xx_init()
288 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_init()
289 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
290 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
291 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_init()
293 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_init()
294 tmp &= PCTL_PWR_OFF; in mvs_64xx_init()
295 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
296 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_init()
298 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_init()
299 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
300 tmp |= PCTL_COM_ON; in mvs_64xx_init()
301 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
302 tmp |= PCTL_LINK_RST; in mvs_64xx_init()
303 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
305 tmp &= ~PCTL_LINK_RST; in mvs_64xx_init()
306 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
315 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); in mvs_64xx_init()
316 tmp &= 0x0000ffff; in mvs_64xx_init()
317 tmp |= 0x00fa0000; in mvs_64xx_init()
318 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); in mvs_64xx_init()
362 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_64xx_init()
363 tmp &= ~PHYEV_SIG_FIS; in mvs_64xx_init()
364 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_64xx_init()
367 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | in mvs_64xx_init()
370 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_64xx_init()
385 tmp = mr32(MVS_PCS); in mvs_64xx_init()
386 tmp |= PCS_CMD_RST; in mvs_64xx_init()
387 tmp &= ~PCS_SELF_CLEAR; in mvs_64xx_init()
388 mw32(MVS_PCS, tmp); in mvs_64xx_init()
393 tmp = 0; in mvs_64xx_init()
399 tmp = 0x10000 | interrupt_coalescing; in mvs_64xx_init()
400 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_init()
411 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | in mvs_64xx_init()
414 mw32(MVS_INT_MASK, tmp); in mvs_64xx_init()
438 u32 tmp; in mvs_64xx_interrupt_enable() local
440 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_enable()
441 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
447 u32 tmp; in mvs_64xx_interrupt_disable() local
449 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_disable()
450 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()
484 u32 tmp; in mvs_64xx_command_active() local
488 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); in mvs_64xx_command_active()
489 } while (tmp & 1 << (slot_idx % 32)); in mvs_64xx_command_active()
491 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); in mvs_64xx_command_active()
492 } while (tmp & 1 << (slot_idx % 32)); in mvs_64xx_command_active()
499 u32 tmp; in mvs_64xx_issue_stop() local
502 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); in mvs_64xx_issue_stop()
503 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_issue_stop()
506 tmp = mr32(MVS_PCS) | 0xFF00; in mvs_64xx_issue_stop()
507 mw32(MVS_PCS, tmp); in mvs_64xx_issue_stop()
513 u32 tmp, offs; in mvs_64xx_free_reg_set() local
520 tmp = mr32(MVS_PCS); in mvs_64xx_free_reg_set()
521 mw32(MVS_PCS, tmp & ~offs); in mvs_64xx_free_reg_set()
523 tmp = mr32(MVS_CTL); in mvs_64xx_free_reg_set()
524 mw32(MVS_CTL, tmp & ~offs); in mvs_64xx_free_reg_set()
527 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); in mvs_64xx_free_reg_set()
528 if (tmp) in mvs_64xx_free_reg_set()
529 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_free_reg_set()
538 u32 tmp, offs; in mvs_64xx_assign_reg_set() local
544 tmp = mr32(MVS_PCS); in mvs_64xx_assign_reg_set()
548 tmp = mr32(MVS_CTL); in mvs_64xx_assign_reg_set()
550 if (!(tmp & offs)) { in mvs_64xx_assign_reg_set()
554 mw32(MVS_PCS, tmp | offs); in mvs_64xx_assign_reg_set()
556 mw32(MVS_CTL, tmp | offs); in mvs_64xx_assign_reg_set()
557 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); in mvs_64xx_assign_reg_set()
558 if (tmp) in mvs_64xx_assign_reg_set()
559 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_assign_reg_set()
623 u32 tmp; in mvs_64xx_phy_work_around() local
626 tmp = mvs_read_port_vsr_data(mvi, i); in mvs_64xx_phy_work_around()
630 tmp &= ~PHY_MODE6_LATECLK; in mvs_64xx_phy_work_around()
632 tmp |= PHY_MODE6_LATECLK; in mvs_64xx_phy_work_around()
633 mvs_write_port_vsr_data(mvi, i, tmp); in mvs_64xx_phy_work_around()
640 u32 tmp; in mvs_64xx_phy_set_link_rate() local
642 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_set_link_rate()
647 tmp &= ~(0xf << 8); in mvs_64xx_phy_set_link_rate()
648 tmp |= lrmin; in mvs_64xx_phy_set_link_rate()
651 tmp &= ~(0xf << 12); in mvs_64xx_phy_set_link_rate()
652 tmp |= lrmax; in mvs_64xx_phy_set_link_rate()
654 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_set_link_rate()
660 u32 tmp; in mvs_64xx_clear_active_cmds() local
662 tmp = mr32(MVS_PCS); in mvs_64xx_clear_active_cmds()
663 mw32(MVS_PCS, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
664 mw32(MVS_PCS, tmp); in mvs_64xx_clear_active_cmds()
665 tmp = mr32(MVS_CTL); in mvs_64xx_clear_active_cmds()
666 mw32(MVS_CTL, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
667 mw32(MVS_CTL, tmp); in mvs_64xx_clear_active_cmds()
756 u32 tmp = 0; in mvs_64xx_tune_interrupt() local
770 tmp = 0x10000 | time; in mvs_64xx_tune_interrupt()
771 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_tune_interrupt()