54 	mw32(MVS_PCS, tmp);  in mvs_64xx_enable_xmt()
71 		mw32(MVS_GBL_PORT_TYPE, 0);  in mvs_64xx_phy_hacks()
114 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_stp_reset()
116 		mw32(MVS_PHY_CTL, reg);  in mvs_64xx_stp_reset()
147 			mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_64xx_clear_srs_irq()
154 			mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));  in mvs_64xx_clear_srs_irq()
166 	mw32(MVS_GBL_CTL, 0);  in mvs_64xx_chip_reset()
185 	mw32(MVS_GBL_CTL, 0);  in mvs_64xx_chip_reset()
227 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_phy_disable()
249 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_phy_enable()
270 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_init()
303 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_init()
306 		mw32(MVS_PHY_CTL, tmp);  in mvs_64xx_init()
311 	mw32(MVS_PCS, 0);		/* MVS_PCS */  in mvs_64xx_init()
321 	mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);  in mvs_64xx_init()
323 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);  in mvs_64xx_init()
324 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);  in mvs_64xx_init()
326 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);  in mvs_64xx_init()
327 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);  in mvs_64xx_init()
329 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);  in mvs_64xx_init()
330 	mw32(MVS_TX_LO, mvi->tx_dma);  in mvs_64xx_init()
331 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);  in mvs_64xx_init()
333 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ);  in mvs_64xx_init()
334 	mw32(MVS_RX_LO, mvi->rx_dma);  in mvs_64xx_init()
335 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);  in mvs_64xx_init()
388 	mw32(MVS_PCS, tmp);  in mvs_64xx_init()
395 		mw32(MVS_INT_COAL, 0x1ff | COAL_EN);  in mvs_64xx_init()
397 		mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);  in mvs_64xx_init()
400 	mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_64xx_init()
403 	mw32(MVS_TX_CFG, 0);  in mvs_64xx_init()
404 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);  in mvs_64xx_init()
405 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);  in mvs_64xx_init()
407 	mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |  in mvs_64xx_init()
414 	mw32(MVS_INT_MASK, tmp);  in mvs_64xx_init()
417 	mw32(MVS_INT_MASK_SRS_0, 0xFFFF);  in mvs_64xx_init()
441 	mw32(MVS_GBL_CTL, tmp | INT_EN);  in mvs_64xx_interrupt_enable()
450 	mw32(MVS_GBL_CTL, tmp & ~INT_EN);  in mvs_64xx_interrupt_disable()
503 		mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_64xx_issue_stop()
505 	mw32(MVS_INT_STAT, CINT_CI_STOP);  in mvs_64xx_issue_stop()
507 	mw32(MVS_PCS, tmp);  in mvs_64xx_issue_stop()
521 		mw32(MVS_PCS, tmp & ~offs);  in mvs_64xx_free_reg_set()
524 		mw32(MVS_CTL, tmp & ~offs);  in mvs_64xx_free_reg_set()
529 		mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_64xx_free_reg_set()
554 				mw32(MVS_PCS, tmp | offs);  in mvs_64xx_assign_reg_set()
556 				mw32(MVS_CTL, tmp | offs);  in mvs_64xx_assign_reg_set()
559 				mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_64xx_assign_reg_set()
663 	mw32(MVS_PCS, tmp & 0xFFFF);  in mvs_64xx_clear_active_cmds()
664 	mw32(MVS_PCS, tmp);  in mvs_64xx_clear_active_cmds()
666 	mw32(MVS_CTL, tmp & 0xFFFF);  in mvs_64xx_clear_active_cmds()
667 	mw32(MVS_CTL, tmp);  in mvs_64xx_clear_active_cmds()
762 		mw32(MVS_INT_COAL, 0);  in mvs_64xx_tune_interrupt()
763 		mw32(MVS_INT_COAL_TMOUT, 0x10000);  in mvs_64xx_tune_interrupt()
766 			mw32(MVS_INT_COAL, 0x1ff|COAL_EN);  in mvs_64xx_tune_interrupt()
768 			mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);  in mvs_64xx_tune_interrupt()
771 		mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_64xx_tune_interrupt()