36 	reg = mr32(MVS_GBL_PORT_TYPE);  in mvs_64xx_detect_porttype()
49 	tmp = mr32(MVS_PCS);  in mvs_64xx_enable_xmt()
95 		reg = mr32(MVS_PHY_CTL);  in mvs_64xx_stp_reset()
144 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
150 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
167 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
186 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
199 		if (!(mr32(MVS_GBL_CTL) & HBA_RST))  in mvs_64xx_chip_reset()
202 	if (mr32(MVS_GBL_CTL) & HBA_RST) {  in mvs_64xx_chip_reset()
225 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_disable()
247 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_enable()
267 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
275 	cctl = mr32(MVS_CTL) & 0xFFFF;  in mvs_64xx_init()
298 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
377 	cctl = mr32(MVS_CTL);  in mvs_64xx_init()
385 	tmp = mr32(MVS_PCS);  in mvs_64xx_init()
440 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_enable()
449 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_disable()
459 		stat = mr32(MVS_GBL_INT_STAT);  in mvs_64xx_isr_status()
502 		tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);  in mvs_64xx_issue_stop()
506 	tmp = mr32(MVS_PCS) | 0xFF00;  in mvs_64xx_issue_stop()
520 		tmp = mr32(MVS_PCS);  in mvs_64xx_free_reg_set()
523 		tmp = mr32(MVS_CTL);  in mvs_64xx_free_reg_set()
527 	tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);  in mvs_64xx_free_reg_set()
544 	tmp = mr32(MVS_PCS);  in mvs_64xx_assign_reg_set()
548 			tmp = mr32(MVS_CTL);  in mvs_64xx_assign_reg_set()
557 			tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);  in mvs_64xx_assign_reg_set()
662 	tmp = mr32(MVS_PCS);  in mvs_64xx_clear_active_cmds()
665 	tmp = mr32(MVS_CTL);  in mvs_64xx_clear_active_cmds()