Lines Matching refs:u32
118 u32 status;
123 u32 initiator_sas_address_hi;
128 u32 initiator_sas_address_lo;
133 u32 reserved;
170 u32 status;
171 u32 remote_initiator_sas_address_hi;
172 u32 remote_initiator_sas_address_lo;
173 u32 remote_initiator;
185 SCU_GEN_VALUE(name, ((u32)1))
961 u32 post_context_port;
963 u32 address_modifier;
964 u32 reserved_08;
965 u32 reserved_0C;
967 u32 interrupt_status;
969 u32 interrupt_mask;
971 u32 interrupt_coalesce_control;
972 u32 reserved_1C;
974 u32 host_task_table_lower;
976 u32 host_task_table_upper;
978 u32 task_context_range;
979 u32 reserved_2C;
981 u32 completion_queue_lower;
983 u32 completion_queue_upper;
984 u32 reserved_38;
985 u32 reserved_3C;
987 u32 completion_queue_put;
989 u32 completion_queue_get;
991 u32 completion_queue_control;
992 u32 reserved_4C;
993 u32 reserved_5x[4];
994 u32 reserved_6x[4];
995 u32 reserved_7x[4];
999 u32 remote_node_context_lower;
1001 u32 remote_node_context_upper;
1002 u32 reserved_88;
1003 u32 reserved_8C;
1005 u32 device_context_capacity;
1007 u32 device_function_capacity;
1009 u32 control_status;
1011 u32 soft_reset_control;
1013 u32 mmr_address_window;
1015 u32 mmr_data_window;
1017 u32 clock_gating_control;
1019 u32 clock_gating_performance;
1021 u32 reserved_Bx[4];
1022 u32 reserved_Cx[4];
1023 u32 reserved_Dx[4];
1024 u32 reserved_Ex[4];
1025 u32 reserved_Fx[4];
1026 u32 reserved_1xx[64];
1027 u32 reserved_2xx[64];
1028 u32 reserved_3xx[64];
1032 u32 task_context_assignment[256];
1058 u32 uf_address_table_lower;
1060 u32 uf_address_table_upper;
1062 u32 uf_header_base_address_lower;
1064 u32 uf_header_base_address_upper;
1066 u32 unsolicited_frame_queue_control;
1068 u32 unsolicited_frame_put_pointer;
1070 u32 unsolicited_frame_get_pointer;
1072 u32 pdma_configuration;
1074 u32 reserved_0020_007C[0x18];
1076 u32 cdma_configuration;
1078 u32 reserved_0084_0400[0xDF];
1129 u32 control;
1131 u32 arbitration_delay_timer;
1133 u32 timer_test_mode;
1135 u32 reserved_0C;
1137 u32 stp_rni;
1139 u32 tlfe_wpo_read_control;
1141 u32 tlfe_wpo_read_data;
1143 u32 rxtl_single_step_control_status_1;
1145 u32 rxtl_single_step_control_status_2;
1147 u32 tlfe_awt_retry_delay_debug_control;
1149 u32 reserved_0028_007F[0x16];
1265 u32 speed_negotiation_timers;
1267 u32 link_layer_status;
1269 u32 port_selector_timeout;
1270 u32 reserved0C;
1272 u32 timeout_unit_value;
1274 u32 rcd_timeout;
1276 u32 link_timer_timeouts;
1278 u32 sas_phy_timeouts;
1280 u32 received_address_frame_error_counter;
1282 u32 invalid_dword_counter;
1284 u32 transmit_identification;
1286 u32 sas_device_name_high;
1288 u32 sas_device_name_low;
1290 u32 source_sas_address_high;
1292 u32 source_sas_address_low;
1294 u32 identify_frame_phy_id;
1296 u32 identify_frame_reserved;
1298 u32 received_address_frame;
1300 u32 maximum_arbitration_wait_timer_timeout;
1302 u32 transmit_primitive;
1304 u32 error_counter_event_notification_control;
1306 u32 frxq_payload_fill_threshold;
1308 u32 link_layer_hang_detection_timeout;
1309 u32 reserved_5C;
1311 u32 received_frame_count;
1313 u32 transmit_frame_count;
1315 u32 received_dword_count;
1317 u32 transmit_dword_count;
1319 u32 loss_of_sync_error_count;
1321 u32 running_disparity_error_count;
1323 u32 received_frame_crc_error_count;
1325 u32 stp_control;
1327 u32 phy_configuration;
1329 u32 clock_skew_management;
1331 u32 transmit_comwake_signal;
1333 u32 transmit_cominit_signal;
1335 u32 transmit_comsas_signal;
1337 u32 cominit_control;
1339 u32 comwake_control;
1341 u32 comsas_control;
1343 u32 received_short_frame_count;
1345 u32 received_frame_without_credit_count;
1347 u32 received_frame_after_done_count;
1349 u32 phy_reset_problem_count;
1351 u32 counter_control;
1353 u32 ssp_timer_timeout_values;
1355 u32 ftx_control;
1357 u32 frx_control;
1359 u32 ftx_watermark;
1361 u32 notify_enable_spinup_control;
1363 u32 sas_training_sequence_timer_values;
1365 u32 phy_capabilities;
1367 u32 phy_control;
1368 u32 reserved_d4;
1370 u32 link_layer_control;
1372 u32 afe_xcvr_control;
1374 u32 afe_lookup_table_control;
1376 u32 phy_source_zone_group_control;
1378 u32 receive_phycap;
1379 u32 reserved_ec;
1381 u32 speed_negotiation_afe_rx_reset_control;
1383 u32 power_management_control;
1385 u32 sas_pm_partial_request_primitive;
1387 u32 sas_pm_slumber_request_primitive;
1389 u32 sas_pm_ack_primitive_register;
1391 u32 sas_pm_nak_primitive_register;
1393 u32 sas_primitive_timeout;
1394 u32 reserved_10c;
1396 u32 pla_product_control[4];
1398 u32 pla_product_sum;
1400 u32 pla_control;
1402 u32 reserved_0128_037f[0x96];
1434 u32 interface_control;
1436 u32 blink_rate;
1438 u32 start_drive_lower;
1440 u32 start_drive_upper;
1442 u32 serial_input_lower;
1444 u32 serial_input_upper;
1446 u32 vendor_specific_code;
1448 u32 reserved_001c;
1450 u32 output_data_select[8];
1452 u32 reserved_1444_14ff[0x30];
1464 u32 registers[256];
1499 u32 control;
1500 u32 status;
1511 u32 control;
1513 u32 real_time_clock;
1515 u32 real_time_clock_control;
1517 u32 reserved_0C;
1533 u32 protocol_engine[4];
1535 u32 tc_scanning_interval_control;
1537 u32 rnc_scanning_interval_control;
1539 u32 reserved_1048_107f[0x0E];
1558 u32 afe_xcvr_control0;
1560 u32 afe_xcvr_control1;
1562 u32 reserved_0008;
1564 u32 afe_dfx_rx_control0;
1566 u32 afe_dfx_rx_control1;
1568 u32 reserved_0014;
1570 u32 afe_dfx_rx_status0;
1572 u32 afe_dfx_rx_status1;
1574 u32 reserved_0020;
1576 u32 afe_tx_control;
1578 u32 afe_tx_amp_control0;
1580 u32 afe_tx_amp_control1;
1582 u32 afe_tx_amp_control2;
1584 u32 afe_tx_amp_control3;
1586 u32 afe_tx_ssc_control;
1588 u32 reserved_003c;
1590 u32 afe_rx_ssc_control0;
1592 u32 afe_rx_ssc_control1;
1594 u32 afe_rx_ssc_control2;
1596 u32 afe_rx_eq_status0;
1598 u32 afe_rx_eq_status1;
1600 u32 afe_rx_cdr_status;
1602 u32 reserved_0058;
1604 u32 afe_channel_control;
1606 u32 reserved_0060_006c[0x04];
1608 u32 afe_xcvr_error_capture_status0;
1610 u32 afe_xcvr_error_capture_status1;
1612 u32 afe_xcvr_error_capture_status2;
1614 u32 afe_xcvr_error_capture_status3;
1616 u32 afe_xcvr_error_capture_status4;
1618 u32 afe_xcvr_error_capture_status5;
1620 u32 reserved_008c_00fc[0x1e];
1631 u32 afe_bias_control;
1632 u32 reserved_0004;
1634 u32 afe_pll_control0;
1636 u32 afe_pll_control1;
1638 u32 afe_pll_control2;
1640 u32 afe_common_block_status;
1642 u32 reserved_18_7c[0x1a];
1644 u32 afe_pmsn_master_control0;
1646 u32 afe_pmsn_master_control1;
1648 u32 afe_pmsn_master_control2;
1650 u32 reserved_008c_00fc[0x1D];
1652 u32 afe_dfx_master_control0;
1654 u32 afe_dfx_master_control1;
1656 u32 afe_dfx_dcl_control;
1658 u32 afe_dfx_digital_monitor_control;
1660 u32 afe_dfx_analog_p_monitor_control;
1662 u32 afe_dfx_analog_n_monitor_control;
1664 u32 afe_dfx_ntl_status;
1666 u32 afe_dfx_fifo_status0;
1668 u32 afe_dfx_fifo_status1;
1670 u32 afe_dfx_master_pattern_control;
1672 u32 afe_dfx_p0_control;
1674 u32 afe_dfx_p0_data[32];
1676 u32 reserved_01ac;
1678 u32 afe_dfx_p0_instruction[24];
1680 u32 reserved_0210;
1682 u32 afe_dfx_p1_control;
1684 u32 afe_dfx_p1_data[16];
1686 u32 reserved_0258_029c[0x12];
1688 u32 afe_dfx_p1_instruction[8];
1690 u32 reserved_02c0_02fc[0x10];
1692 u32 afe_dfx_tx_pmsn_control;
1694 u32 afe_dfx_rx_pmsn_control;
1695 u32 reserved_0308;
1697 u32 afe_dfx_noa_control0;
1699 u32 afe_dfx_noa_control1;
1701 u32 afe_dfx_noa_control2;
1703 u32 afe_dfx_noa_control3;
1705 u32 afe_dfx_noa_control4;
1707 u32 afe_dfx_noa_control5;
1709 u32 afe_dfx_noa_control6;
1711 u32 afe_dfx_noa_control7;
1713 u32 reserved_032c_07fc[0x135];
1719 u32 reserved_0c00_0ffc[0x0100];
1723 u32 table[0xE0];
1728 u32 table[256];
1738 u32 table[2048];
1748 u32 ram[128];
1758 u32 ram[128];
1769 u32 ram[scu_scratch_ram_SIZE_IN_DWORDS];
1778 u32 reserved[64];
1787 u32 reserved[64];
1796 u32 reserved[64];
1823 u32 reserved_01500_1BFF[0x1C0];
1844 u32 reserved_6800_69FF[0x80];
1848 u32 reserved_6d00_7fff[0x4c0];
1857 u32 reserved_f000_211fff[0x80c00];