Lines Matching refs:mem_ptr
2057 (unsigned long)ha->mem_ptr); in ips_host_info()
2260 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2264 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_get_bios_version()
2267 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2271 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_get_bios_version()
2275 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2279 major = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2282 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2285 minor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2288 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2291 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
4270 if (ha->mem_ptr) { in ips_free()
4273 ha->mem_ptr = NULL; in ips_free()
4517 isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isinit_copperhead_memio()
4518 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); in ips_isinit_copperhead_memio()
4546 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_isinit_morpheus()
4547 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isinit_morpheus()
4675 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_enable_int_copperhead_memio()
4676 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ in ips_enable_int_copperhead_memio()
4694 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4696 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4697 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ in ips_enable_int_morpheus()
4816 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4828 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4829 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4842 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4854 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4855 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4859 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); in ips_init_copperhead_memio()
4873 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); in ips_init_copperhead_memio()
4876 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); in ips_init_copperhead_memio()
4880 writel(0, ha->mem_ptr + IPS_REG_NDAE); in ips_init_copperhead_memio()
4883 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4911 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4928 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4936 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4939 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4956 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4967 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4984 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_morpheus()
4988 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4991 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
4993 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
5075 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5080 writeb(0, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5121 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); in ips_reset_morpheus()
5192 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); in ips_statinit_memio()
5194 ha->mem_ptr + IPS_REG_SQER); in ips_statinit_memio()
5195 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); in ips_statinit_memio()
5196 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); in ips_statinit_memio()
5251 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); in ips_statupd_copperhead_memio()
5272 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); in ips_statupd_morpheus()
5362 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { in ips_issue_copperhead_memio()
5378 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); in ips_issue_copperhead_memio()
5379 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); in ips_issue_copperhead_memio()
5443 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); in ips_issue_i2o_memio()
5497 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5508 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5530 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isintr_morpheus()
6188 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6192 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6197 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6202 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6207 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6215 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6219 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6233 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6241 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6245 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6269 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6274 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6394 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6398 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6402 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6410 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6414 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6425 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6429 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6439 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6443 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6452 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6456 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6530 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6534 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_verify_bios_memio()
6537 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6540 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_verify_bios_memio()
6546 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6551 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); in ips_verify_bios_memio()
6898 char __iomem *mem_ptr; in ips_init_phase1() local
6946 mem_ptr = ioremap_ptr + offs; in ips_init_phase1()
6949 mem_ptr = NULL; in ips_init_phase1()
6969 ha->mem_ptr = mem_ptr; in ips_init_phase1()
7069 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_phase1()