150 static u64 mv_outbound_read(struct hpt_iopmu_mv __iomem *mu)  in mv_outbound_read()  argument
152 	u32 outbound_tail = readl(&mu->outbound_tail);  in mv_outbound_read()
153 	u32 outbound_head = readl(&mu->outbound_head);  in mv_outbound_read()
158 		memcpy_fromio(&p, &mu->outbound_q[mu->outbound_tail], 8);  in mv_outbound_read()
163 		writel(outbound_tail, &mu->outbound_tail);  in mv_outbound_read()
171 	u32 inbound_head = readl(&hba->u.mv.mu->inbound_head);  in mv_inbound_write()
177 	memcpy_toio(&hba->u.mv.mu->inbound_q[inbound_head], &p, 8);  in mv_inbound_write()
178 	writel(head, &hba->u.mv.mu->inbound_head);  in mv_inbound_write()
221 		msg = readl(&hba->u.mv.mu->outbound_msg);  in iop_intr_mv()
230 		while ((tag = mv_outbound_read(hba->u.mv.mu)))  in iop_intr_mv()
267 		writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));  in iop_intr_mvfrey()
269 	status = readl(&(hba->u.mvfrey.mu->f0_doorbell));  in iop_intr_mvfrey()
271 		writel(status, &(hba->u.mvfrey.mu->f0_doorbell));  in iop_intr_mvfrey()
273 			u32 msg = readl(&(hba->u.mvfrey.mu->cpu_to_f0_msg_a));  in iop_intr_mvfrey()
280 	status = readl(&(hba->u.mvfrey.mu->isr_cause));  in iop_intr_mvfrey()
282 		writel(status, &(hba->u.mvfrey.mu->isr_cause));  in iop_intr_mvfrey()
301 		writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));  in iop_intr_mvfrey()
376 	writel(msg, &hba->u.mv.mu->inbound_msg);  in hptiop_post_msg_mv()
383 	writel(msg, &(hba->u.mvfrey.mu->f0_to_cpu_msg_a));  in hptiop_post_msg_mvfrey()
384 	readl(&(hba->u.mvfrey.mu->f0_to_cpu_msg_a));  in hptiop_post_msg_mvfrey()
571 	writel(CPU_TO_F0_DRBL_MSG_BIT, &(hba->u.mvfrey.mu->f0_doorbell_enable));  in hptiop_enable_intr_mvfrey()
572 	writel(0x1, &(hba->u.mvfrey.mu->isr_enable));  in hptiop_enable_intr_mvfrey()
573 	writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));  in hptiop_enable_intr_mvfrey()
649 	hba->u.mv.mu = hptiop_map_pci_bar(hba, 2);  in hptiop_map_pci_bar_mv()
650 	if (hba->u.mv.mu == NULL) {  in hptiop_map_pci_bar_mv()
664 	hba->u.mvfrey.mu = hptiop_map_pci_bar(hba, 2);  in hptiop_map_pci_bar_mvfrey()
665 	if (hba->u.mvfrey.mu == NULL) {  in hptiop_map_pci_bar_mvfrey()
676 	iounmap(hba->u.mv.mu);  in hptiop_unmap_pci_bar_mv()
682 	iounmap(hba->u.mvfrey.mu);  in hptiop_unmap_pci_bar_mvfrey()
960 		&(hba->u.mvfrey.mu->inbound_write_ptr));  in hptiop_post_req_mvfrey()
961 	readl(&(hba->u.mvfrey.mu->inbound_write_ptr));  in hptiop_post_req_mvfrey()
985 			&(hba->u.mvfrey.mu->inbound_base));  in hptiop_reset_comm_mvfrey()
987 			&(hba->u.mvfrey.mu->inbound_base_high));  in hptiop_reset_comm_mvfrey()
990 			&(hba->u.mvfrey.mu->outbound_base));  in hptiop_reset_comm_mvfrey()
992 			&(hba->u.mvfrey.mu->outbound_base_high));  in hptiop_reset_comm_mvfrey()
995 			&(hba->u.mvfrey.mu->outbound_shadow_base));  in hptiop_reset_comm_mvfrey()
997 			&(hba->u.mvfrey.mu->outbound_shadow_base_high));  in hptiop_reset_comm_mvfrey()
1211 	u32 list_count = readl(&hba->u.mvfrey.mu->inbound_conf_ctl);  in hptiop_internal_memalloc_mvfrey()
1550 	writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable));  in hptiop_disable_intr_mvfrey()
1551 	readl(&(hba->u.mvfrey.mu->f0_doorbell_enable));  in hptiop_disable_intr_mvfrey()
1552 	writel(0, &(hba->u.mvfrey.mu->isr_enable));  in hptiop_disable_intr_mvfrey()
1553 	readl(&(hba->u.mvfrey.mu->isr_enable));  in hptiop_disable_intr_mvfrey()
1554 	writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));  in hptiop_disable_intr_mvfrey()
1555 	readl(&(hba->u.mvfrey.mu->pcie_f0_int_enable));  in hptiop_disable_intr_mvfrey()