163 	void __iomem *vaddr;  member
411 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
412 	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
418 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_no_read()
424 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_ioaccel2()
436 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
437 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
441 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
442 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
450 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
451 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
455 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
456 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
470 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
471 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
475 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
501 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
522 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
528 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
534 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()
542 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_ioaccel_mode1_intr_pending()
572 		writel((q << 24) | rq->current_entry, h->vaddr +  in SA5_ioaccel_mode1_completed()