Lines Matching refs:rb
192 void __iomem *rb; in bfa_ioc_ct_reg_init() local
195 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
197 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
198 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
199 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
202 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
203 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
204 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
205 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
206 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
207 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
208 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
210 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); in bfa_ioc_ct_reg_init()
211 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); in bfa_ioc_ct_reg_init()
212 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
213 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
214 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
215 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
216 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
222 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); in bfa_ioc_ct_reg_init()
223 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); in bfa_ioc_ct_reg_init()
224 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_reg_init()
225 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_reg_init()
230 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); in bfa_ioc_ct_reg_init()
231 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG); in bfa_ioc_ct_reg_init()
232 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); in bfa_ioc_ct_reg_init()
233 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT); in bfa_ioc_ct_reg_init()
234 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC); in bfa_ioc_ct_reg_init()
239 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); in bfa_ioc_ct_reg_init()
245 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
251 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
254 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
256 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
257 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
258 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
259 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
260 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
261 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
264 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
265 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
266 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
267 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
268 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
270 ioc->ioc_regs.heartbeat = (rb + CT2_BFA_IOC1_HBEAT_REG); in bfa_ioc_ct2_reg_init()
271 ioc->ioc_regs.ioc_fwstate = (rb + CT2_BFA_IOC1_STATE_REG); in bfa_ioc_ct2_reg_init()
272 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
273 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
274 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
280 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); in bfa_ioc_ct2_reg_init()
281 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); in bfa_ioc_ct2_reg_init()
282 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_reg_init()
283 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_reg_init()
288 ioc->ioc_regs.ioc_sem_reg = (rb + CT2_HOST_SEM0_REG); in bfa_ioc_ct2_reg_init()
289 ioc->ioc_regs.ioc_usage_sem_reg = (rb + CT2_HOST_SEM1_REG); in bfa_ioc_ct2_reg_init()
290 ioc->ioc_regs.ioc_init_sem_reg = (rb + CT2_HOST_SEM2_REG); in bfa_ioc_ct2_reg_init()
291 ioc->ioc_regs.ioc_usage_reg = (rb + CT2_BFA_FW_USE_COUNT); in bfa_ioc_ct2_reg_init()
292 ioc->ioc_regs.ioc_fail_sync = (rb + CT2_BFA_IOC_FAIL_SYNC); in bfa_ioc_ct2_reg_init()
297 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); in bfa_ioc_ct2_reg_init()
303 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct2_reg_init()
314 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
320 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
331 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
334 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
347 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
350 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
371 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
571 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_poweron() local
574 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_ioc_ct2_poweron()
577 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_ioc_ct2_poweron()
583 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_ioc_ct2_poweron()
585 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_ioc_ct2_poweron()
589 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode) in bfa_ioc_ct_pll_init() argument
604 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
606 __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
608 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
609 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
611 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
612 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
613 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
614 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
615 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
616 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
617 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
618 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
620 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
622 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
624 __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
626 __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
627 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
629 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
630 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
631 writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
632 writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
635 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
636 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
638 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
640 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
643 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
644 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
647 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
649 r32 = readl((rb + MBIST_STAT_REG)); in bfa_ioc_ct_pll_init()
650 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
655 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
662 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
666 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
672 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
674 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
679 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
680 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
682 r32 = readl((rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
683 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
688 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
691 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
700 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
707 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
711 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
716 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
717 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
722 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
723 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
728 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
731 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
740 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
744 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
746 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
749 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
751 writel(0, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
755 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
759 rb + CT2_CSI_MAC_CONTROL_REG(0)); in bfa_ioc_ct2_mac_reset()
761 rb + CT2_CSI_MAC_CONTROL_REG(1)); in bfa_ioc_ct2_mac_reset()
765 bfa_ioc_ct2_enable_flash(void __iomem *rb) in bfa_ioc_ct2_enable_flash() argument
769 r32 = readl((rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_enable_flash()
770 writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_enable_flash()
771 r32 = readl((rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_enable_flash()
772 writel(r32 | 1, (rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_enable_flash()
782 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
786 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
794 bfa_ioc_ct2_nfc_halt(void __iomem *rb) in bfa_ioc_ct2_nfc_halt() argument
798 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halt()
800 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_nfc_halt()
804 WARN_ON(!bfa_ioc_ct2_nfc_halted(rb)); in bfa_ioc_ct2_nfc_halt()
808 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
813 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
815 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
824 bfa_ioc_ct2_clk_reset(void __iomem *rb) in bfa_ioc_ct2_clk_reset() argument
828 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_clk_reset()
829 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_clk_reset()
834 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
836 (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
838 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
840 (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
845 bfa_ioc_ct2_nfc_clk_reset(void __iomem *rb) in bfa_ioc_ct2_nfc_clk_reset() argument
849 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_nfc_clk_reset()
851 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_nfc_clk_reset()
853 writel(__RESET_AND_START_SCLK_LCLK_PLLS, rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_nfc_clk_reset()
856 r32 = readl(rb + CT2_NFC_FLASH_STS_REG); in bfa_ioc_ct2_nfc_clk_reset()
864 r32 = readl(rb + CT2_NFC_FLASH_STS_REG); in bfa_ioc_ct2_nfc_clk_reset()
871 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_nfc_clk_reset()
876 bfa_ioc_ct2_wait_till_nfc_running(void __iomem *rb) in bfa_ioc_ct2_wait_till_nfc_running() argument
881 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_wait_till_nfc_running()
882 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_wait_till_nfc_running()
884 r32 = readl(rb + CT2_NFC_STS_REG); in bfa_ioc_ct2_wait_till_nfc_running()
890 r32 = readl(rb + CT2_NFC_STS_REG); in bfa_ioc_ct2_wait_till_nfc_running()
895 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode) in bfa_ioc_ct2_pll_init() argument
899 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
905 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
906 bfa_ioc_ct2_enable_flash(rb); in bfa_ioc_ct2_pll_init()
908 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
910 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
911 bfa_ioc_ct2_enable_flash(rb); in bfa_ioc_ct2_pll_init()
914 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
919 bfa_ioc_ct2_wait_till_nfc_running(rb); in bfa_ioc_ct2_pll_init()
921 bfa_ioc_ct2_nfc_clk_reset(rb); in bfa_ioc_ct2_pll_init()
923 bfa_ioc_ct2_nfc_halt(rb); in bfa_ioc_ct2_pll_init()
925 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
926 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
927 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
939 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_pll_init()
940 writel((r32 & 0xfbffffff), (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_pll_init()
947 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
948 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
951 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
953 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
955 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
956 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
958 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
960 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
961 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
965 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
967 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); in bfa_ioc_ct2_pll_init()
968 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); in bfa_ioc_ct2_pll_init()