795 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_init()
796 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_init()
797 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_init()
798 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_init()
1157 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_dma_complete()
1158 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_dma_complete()
1331 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_select()
1337 	NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);  in NCR5380_select()
1338 	NCR5380_write(MODE_REG, MR_ARBITRATE);  in NCR5380_select()
1352 			NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1353 			NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1366 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1383 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1392 	NCR5380_write(INITIATOR_COMMAND_REG,  in NCR5380_select()
1397 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1398 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1417 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1418 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1429 	NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << cmd->device->id)));  in NCR5380_select()
1437 	NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY |  in NCR5380_select()
1439 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1447 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1451 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_select()
1460 	NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA |  in NCR5380_select()
1510 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1514 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1530 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_select()
1533 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1539 			NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1547 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1549 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1648 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));  in NCR5380_transfer_pio()
1669 			NCR5380_write(OUTPUT_DATA_REG, *d);  in NCR5380_transfer_pio()
1684 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);  in NCR5380_transfer_pio()
1686 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_transfer_pio()
1689 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_transfer_pio()
1692 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_transfer_pio()
1697 			NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);  in NCR5380_transfer_pio()
1718 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_transfer_pio()
1720 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_transfer_pio()
1759 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1774 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));  in do_abort()
1777 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |  in do_abort()
1781 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1848 		NCR5380_write(TARGET_COMMAND_REG, 1);  in NCR5380_transfer_dma()
1850 		NCR5380_write(INITIATOR_COMMAND_REG, 0);  in NCR5380_transfer_dma()
1851 		NCR5380_write(MODE_REG,  in NCR5380_transfer_dma()
1853 		NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);  in NCR5380_transfer_dma()
1855 		NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_transfer_dma()
1857 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_DATA);  in NCR5380_transfer_dma()
1858 		NCR5380_write(MODE_REG,  in NCR5380_transfer_dma()
1860 		NCR5380_write(START_DMA_SEND_REG, 0);  in NCR5380_transfer_dma()
1887 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));  in NCR5380_transfer_dma()
1890 	NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_ENABLE_EOP_INTR | MR_MONITOR_BSY);  in NCR5380_transfer_dma()
1905 		NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);  in NCR5380_transfer_dma()
1907 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);  in NCR5380_transfer_dma()
1908 		NCR5380_write(START_DMA_SEND_REG, 0);  in NCR5380_transfer_dma()
2000 				NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));  in NCR5380_information_transfer()
2002 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |  in NCR5380_information_transfer()
2006 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_information_transfer()
2075 						NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |  in NCR5380_information_transfer()
2108 				NCR5380_write(SELECT_ENABLE_REG, 0);	/* disable reselects */  in NCR5380_information_transfer()
2127 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2133 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2164 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2194 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2240 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2245 					NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_information_transfer()
2261 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2263 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2286 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2302 					NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_information_transfer()
2305 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2326 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2328 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2345 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2359 						NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_information_transfer()
2407 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_information_transfer()
2425 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_information_transfer()
2490 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_reselect()
2506 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);  in NCR5380_reselect()
2510 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2521 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));  in NCR5380_reselect()
2548 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2622 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);  in NCR5380_reselect()
2626 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2636 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_reselect()
2883 	NCR5380_write(TARGET_COMMAND_REG,  in NCR5380_bus_reset()
2886 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST);  in NCR5380_bus_reset()
2889 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_bus_reset()
2890 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_bus_reset()
2891 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_bus_reset()
2892 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_bus_reset()