86 #define REG0 (outb(C4_IMG, CONFIG4))
87 #define REG1 (outb(C5_IMG, CONFIG5))
102   outb(count & 0xff, TC_LSB); \
103   outb((count >> 8) & 0xff, TC_MSB); \
104   outb((count >> 16) & 0xff, TC_HIGH);
153 #define rtrc(i) {inb(0x3da);outb(0x31,0x3c0);outb((i),0x3c0);}
441 					outb(*request++, PIO_FIFO);  in NCR53c406a_pio_write()
491 				outb(C5_IMG, ports[i] + 0x0d);	/* reg set 1 */  in NCR53c406a_detect()
717 	outb(scmd_id(SCpnt), DEST_ID);	/* set destination */  in NCR53c406a_queue_lck()
718 	outb(FLUSH_FIFO, CMD_REG);	/* reset the fifos */  in NCR53c406a_queue_lck()
721 		outb(SCpnt->cmnd[i], SCSI_FIFO);  in NCR53c406a_queue_lck()
723 	outb(SELECT_NO_ATN, CMD_REG);  in NCR53c406a_queue_lck()
737 	outb(C4_IMG, CONFIG4);	/* Select reg set 0 */  in DEF_SCSI_QCMD()
738 	outb(CHIP_RESET, CMD_REG);  in DEF_SCSI_QCMD()
739 	outb(SCSI_NOP, CMD_REG);	/* required after reset */  in DEF_SCSI_QCMD()
740 	outb(SCSI_RESET, CMD_REG);  in DEF_SCSI_QCMD()
870 			outb(FLUSH_FIFO, CMD_REG);  in NCR53c406a_intr()
877 			outb(TRANSFER_INFO | DMA_OP, CMD_REG);  in NCR53c406a_intr()
892 			outb(FLUSH_FIFO, CMD_REG);  in NCR53c406a_intr()
898 			outb(TRANSFER_INFO | DMA_OP, CMD_REG);  in NCR53c406a_intr()
917 		outb(FLUSH_FIFO, CMD_REG);  in NCR53c406a_intr()
918 		outb(INIT_CMD_COMPLETE, CMD_REG);  in NCR53c406a_intr()
929 		outb(SET_ATN, CMD_REG);	/* Reject the message */  in NCR53c406a_intr()
930 		outb(MSG_ACCEPT, CMD_REG);  in NCR53c406a_intr()
945 			outb(SET_ATN, CMD_REG);	/* Reject message */  in NCR53c406a_intr()
948 		outb(MSG_ACCEPT, CMD_REG);  in NCR53c406a_intr()
964 	outb(0xff, CMD_REG);  in irq_probe()
978 	outb(CHIP_RESET, CMD_REG);  in irq_probe()
979 	outb(SCSI_NOP, CMD_REG);  in irq_probe()
990 	outb(0x00, PIO_STATUS);  in chip_init()
992 	outb(0x01, PIO_STATUS);  in chip_init()
994 	outb(0x00, PIO_FLAG);  in chip_init()
996 	outb(C4_IMG, CONFIG4);	/* REG0; */  in chip_init()
997 	outb(C3_IMG, CONFIG3);  in chip_init()
998 	outb(C2_IMG, CONFIG2);  in chip_init()
999 	outb(C1_IMG, CONFIG1);  in chip_init()
1001 	outb(0x05, CLKCONV);	/* clock conversion factor */  in chip_init()
1002 	outb(0x9C, SRTIMOUT);	/* Selection timeout */  in chip_init()
1003 	outb(0x05, SYNCPRD);	/* Synchronous transfer period */  in chip_init()
1004 	outb(SYNC_MODE, SYNCOFF);	/* synchronous mode */  in chip_init()