592 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_probe_irq()
593 	NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_probe_irq()
594 	NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);  in NCR5380_probe_irq()
595 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL);  in NCR5380_probe_irq()
600 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_probe_irq()
601 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_probe_irq()
841 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_init()
842 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_init()
843 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_init()
844 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_init()
848 		NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE);  in NCR5380_init()
1157 					NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_intr()
1158 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_intr()
1231 	NCR5380_write(TARGET_COMMAND_REG, 0);  in NCR5380_select()
1237 	NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);  in NCR5380_select()
1238 	NCR5380_write(MODE_REG, MR_ARBITRATE);  in NCR5380_select()
1248 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1249 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1266 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1270 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_SEL);  in NCR5380_select()
1278 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1279 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1297 	NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << scmd_id(cmd))));  in NCR5380_select()
1305 …NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY | ICR_ASSERT_DATA | ICR_ASSERT_ATN…  in NCR5380_select()
1306 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1312 	NCR5380_write(SELECT_ENABLE_REG, 0);  in NCR5380_select()
1321 …NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_ATN | ICR_ASSERT_SEL…  in NCR5380_select()
1377 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1380 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1391 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_select()
1394 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_select()
1400 			NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1405 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1407 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1435 		NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);  in NCR5380_select()
1512 	 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));  in NCR5380_transfer_pio()
1549 			NCR5380_write(OUTPUT_DATA_REG, *d);  in NCR5380_transfer_pio()
1564 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);  in NCR5380_transfer_pio()
1566 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_ACK);  in NCR5380_transfer_pio()
1568 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_ATN);  in NCR5380_transfer_pio()
1570 …NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_ATN | ICR_ASSERT_ACK);  in NCR5380_transfer_pio()
1574 			NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);  in NCR5380_transfer_pio()
1594 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in NCR5380_transfer_pio()
1596 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_transfer_pio()
1630 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));  in do_reset()
1631 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST);  in do_reset()
1633 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in do_reset()
1657 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1676 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));  in do_abort()
1679 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN | ICR_ASSERT_ACK);  in do_abort()
1681 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);  in do_abort()
1751 	NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));  in NCR5380_transfer_dma()
1754 	NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_ENABLE_EOP_INTR | MR_MONITOR_BSY);  in NCR5380_transfer_dma()
1756 	NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE);  in NCR5380_transfer_dma()
1769 		NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE |  in NCR5380_transfer_dma()
1773 		NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE);  in NCR5380_transfer_dma()
1785 		NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);  in NCR5380_transfer_dma()
1788 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);  in NCR5380_transfer_dma()
1790 		NCR5380_write(START_DMA_SEND_REG, 0);  in NCR5380_transfer_dma()
1855 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_transfer_dma()
1856 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_transfer_dma()
1960 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_transfer_dma()
1961 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);  in NCR5380_transfer_dma()
2029 				NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
2031 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN | ICR_ASSERT_ACK);
2033 				NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2103 						NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2137 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2163 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2209 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2214 					NCR5380_write(TARGET_COMMAND_REG, 0);
2221 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2234 						NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2246 						NCR5380_write(TARGET_COMMAND_REG, 0);
2249 						NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2269 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2286 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2298 						NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2339 					NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2353 					NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2426 	NCR5380_write(MODE_REG, MR_BASE);
2441 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);
2447 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2468 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2546 	NCR5380_write(MODE_REG, MR_BASE);
2547 	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2613 		NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_ATN);