415 	mr = NCR5380_read(MODE_REG);  in NCR5380_print()
842 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_init()
1141 …if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & BASR_END_DMA_TRANSFER) || !(basr & BASR_PHASE_MA…  in NCR5380_intr()
1157 					NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_intr()
1161 …: unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(ST…  in NCR5380_intr()
1238 	NCR5380_write(MODE_REG, MR_ARBITRATE);  in NCR5380_select()
1248 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1266 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1278 		NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1306 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_select()
1754 	NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_ENABLE_EOP_INTR | MR_MONITOR_BSY);  in NCR5380_transfer_dma()
1756 	NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE);  in NCR5380_transfer_dma()
1769 		NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE |  in NCR5380_transfer_dma()
1773 		NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE);  in NCR5380_transfer_dma()
1776 	dprintk(NDEBUG_DMA, "scsi%d : mode reg = 0x%X\n", instance->host_no, NCR5380_read(MODE_REG));  in NCR5380_transfer_dma()
1855 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_transfer_dma()
1960 	NCR5380_write(MODE_REG, MR_BASE);  in NCR5380_transfer_dma()
2426 	NCR5380_write(MODE_REG, MR_BASE);
2546 	NCR5380_write(MODE_REG, MR_BASE);