Lines Matching refs:DSR
64 #define DSR 0x14 /* Status Reg */ macro
286 di_write_busy_wait(imxdi, DSR_CAF, DSR); in di_handle_valid_state()
336 di_write_busy_wait(imxdi, DSR_NVF, DSR); in di_handle_invalid_state()
338 di_write_busy_wait(imxdi, DSR_TCO, DSR); in di_handle_invalid_state()
345 return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); in di_handle_invalid_state()
388 DSR_MCO | DSR_TCO), DSR); in di_handle_invalid_and_failure_state()
390 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
402 di_write_busy_wait(imxdi, DSR_SVF, DSR); in di_handle_invalid_and_failure_state()
405 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
426 dsr = readl(imxdi->ioaddr + DSR); in di_handle_state()
490 writel(DSR_WEF, imxdi->ioaddr + DSR); in clear_write_error()
494 if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) in clear_write_error()
573 dsr = readl(imxdi->ioaddr + DSR); in dryice_rtc_set_mmss()
632 alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; in dryice_rtc_read_alarm()
689 dsr = readl(imxdi->ioaddr + DSR); in dryice_norm_irq()
755 di_write_wait(imxdi, DSR_CAF, DSR); in dryice_work()