Lines Matching refs:rdev
217 idtg2_em_init(struct rio_dev *rdev) in idtg2_em_init() argument
227 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); in idtg2_em_init()
230 rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); in idtg2_em_init()
237 rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, in idtg2_em_init()
244 rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); in idtg2_em_init()
245 rio_write_config_32(rdev, IDT_DEV_CTRL_1, in idtg2_em_init()
253 rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); in idtg2_em_init()
256 rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, in idtg2_em_init()
260 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); in idtg2_em_init()
262 rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); in idtg2_em_init()
263 rio_write_config_32(rdev, in idtg2_em_init()
270 rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); in idtg2_em_init()
277 rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); in idtg2_em_init()
282 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; in idtg2_em_init()
284 rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); in idtg2_em_init()
285 rio_write_config_32(rdev, IDT_LANE_CTRL(i), in idtg2_em_init()
294 rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); in idtg2_em_init()
297 rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); in idtg2_em_init()
300 rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); in idtg2_em_init()
303 rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); in idtg2_em_init()
304 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); in idtg2_em_init()
311 rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); in idtg2_em_init()
314 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); in idtg2_em_init()
315 rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, in idtg2_em_init()
319 rio_write_config_32(rdev, in idtg2_em_init()
320 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); in idtg2_em_init()
326 idtg2_em_handler(struct rio_dev *rdev, u8 portnum) in idtg2_em_handler() argument
330 rio_read_config_32(rdev, in idtg2_em_handler()
331 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); in idtg2_em_handler()
336 rio_read_config_32(rdev, in idtg2_em_handler()
341 rio_name(rdev), em_ltlerrdet, regval); in idtg2_em_handler()
344 rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); in idtg2_em_handler()
349 rio_read_config_32(rdev, in idtg2_em_handler()
350 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); in idtg2_em_handler()
357 rio_read_config_32(rdev, in idtg2_em_handler()
361 " errors 0x%x\n", rio_name(rdev), regval); in idtg2_em_handler()
364 rio_write_config_32(rdev, in idtg2_em_handler()
375 struct rio_dev *rdev = to_rio_dev(dev); in idtg2_show_errlog() local
379 while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) { in idtg2_show_errlog()
393 static int idtg2_sysfs(struct rio_dev *rdev, bool create) in idtg2_sysfs() argument
395 struct device *dev = &rdev->dev; in idtg2_sysfs()
420 static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id) in idtg2_probe() argument
422 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); in idtg2_probe()
424 spin_lock(&rdev->rswitch->lock); in idtg2_probe()
426 if (rdev->rswitch->ops) { in idtg2_probe()
427 spin_unlock(&rdev->rswitch->lock); in idtg2_probe()
431 rdev->rswitch->ops = &idtg2_switch_ops; in idtg2_probe()
433 if (rdev->do_enum) { in idtg2_probe()
435 rio_write_config_32(rdev, in idtg2_probe()
440 idtg2_sysfs(rdev, true); in idtg2_probe()
442 spin_unlock(&rdev->rswitch->lock); in idtg2_probe()
446 static void idtg2_remove(struct rio_dev *rdev) in idtg2_remove() argument
448 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); in idtg2_remove()
449 spin_lock(&rdev->rswitch->lock); in idtg2_remove()
450 if (rdev->rswitch->ops != &idtg2_switch_ops) { in idtg2_remove()
451 spin_unlock(&rdev->rswitch->lock); in idtg2_remove()
454 rdev->rswitch->ops = NULL; in idtg2_remove()
457 idtg2_sysfs(rdev, false); in idtg2_remove()
459 spin_unlock(&rdev->rswitch->lock); in idtg2_remove()