321 	u32 rval;  in tsi721_pw_enable()  local
323 	rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);  in tsi721_pw_enable()
326 		rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;  in tsi721_pw_enable()
328 		rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;  in tsi721_pw_enable()
334 	iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);  in tsi721_pw_enable()
1175 	u32 rval;  in tsi721_imsg_interrupt_enable()  local
1184 	rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_enable()
1185 	iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_enable()
1195 	rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_imsg_interrupt_enable()
1196 	iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),  in tsi721_imsg_interrupt_enable()
1205 	u32 rval;  in tsi721_imsg_interrupt_disable()  local
1214 	rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_disable()
1215 	rval &= ~inte_mask;  in tsi721_imsg_interrupt_disable()
1216 	iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_disable()
1226 	rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_imsg_interrupt_disable()
1227 	rval &= ~TSI721_INT_IMSG_CHAN(ch);  in tsi721_imsg_interrupt_disable()
1228 	iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_imsg_interrupt_disable()
1236 	u32 rval;  in tsi721_omsg_interrupt_enable()  local
1245 	rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_enable()
1246 	iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_enable()
1256 	rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_omsg_interrupt_enable()
1257 	iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),  in tsi721_omsg_interrupt_enable()
1266 	u32 rval;  in tsi721_omsg_interrupt_disable()  local
1275 	rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_disable()
1276 	rval &= ~inte_mask;  in tsi721_omsg_interrupt_disable()
1277 	iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_disable()
1287 	rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_omsg_interrupt_disable()
1288 	rval &= ~TSI721_INT_OMSG_CHAN(ch);  in tsi721_omsg_interrupt_disable()
1289 	iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);  in tsi721_omsg_interrupt_disable()