Lines Matching refs:mmio_base
54 void __iomem *mmio_base; member
87 u32 max = readl(imx->mmio_base + MX1_PWMP); in imx_pwm_config_v1()
89 writel(max - p, imx->mmio_base + MX1_PWMS); in imx_pwm_config_v1()
99 val = readl(imx->mmio_base + MX1_PWMC); in imx_pwm_set_enable_v1()
106 writel(val, imx->mmio_base + MX1_PWMC); in imx_pwm_set_enable_v1()
129 sr = readl(imx->mmio_base + MX3_PWMSR); in imx_pwm_config_v2()
136 sr = readl(imx->mmio_base + MX3_PWMSR); in imx_pwm_config_v2()
141 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); in imx_pwm_config_v2()
144 cr = readl(imx->mmio_base + MX3_PWMCR); in imx_pwm_config_v2()
173 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); in imx_pwm_config_v2()
174 writel(period_cycles, imx->mmio_base + MX3_PWMPR); in imx_pwm_config_v2()
183 writel(cr, imx->mmio_base + MX3_PWMCR); in imx_pwm_config_v2()
193 val = readl(imx->mmio_base + MX3_PWMCR); in imx_pwm_set_enable_v2()
200 writel(val, imx->mmio_base + MX3_PWMCR); in imx_pwm_set_enable_v2()
310 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); in imx_pwm_probe()
311 if (IS_ERR(imx->mmio_base)) in imx_pwm_probe()
312 return PTR_ERR(imx->mmio_base); in imx_pwm_probe()