68 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_config_v1()  local
87 	u32 max = readl(imx->mmio_base + MX1_PWMP);  in imx_pwm_config_v1()
89 	writel(max - p, imx->mmio_base + MX1_PWMS);  in imx_pwm_config_v1()
96 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_set_enable_v1()  local
99 	val = readl(imx->mmio_base + MX1_PWMC);  in imx_pwm_set_enable_v1()
106 	writel(val, imx->mmio_base + MX1_PWMC);  in imx_pwm_set_enable_v1()
112 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_config_v2()  local
129 		sr = readl(imx->mmio_base + MX3_PWMSR);  in imx_pwm_config_v2()
136 			sr = readl(imx->mmio_base + MX3_PWMSR);  in imx_pwm_config_v2()
141 		writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);  in imx_pwm_config_v2()
144 			cr = readl(imx->mmio_base + MX3_PWMCR);  in imx_pwm_config_v2()
152 	c = clk_get_rate(imx->clk_per);  in imx_pwm_config_v2()
173 	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);  in imx_pwm_config_v2()
174 	writel(period_cycles, imx->mmio_base + MX3_PWMPR);  in imx_pwm_config_v2()
183 	writel(cr, imx->mmio_base + MX3_PWMCR);  in imx_pwm_config_v2()
190 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_set_enable_v2()  local
193 	val = readl(imx->mmio_base + MX3_PWMCR);  in imx_pwm_set_enable_v2()
200 	writel(val, imx->mmio_base + MX3_PWMCR);  in imx_pwm_set_enable_v2()
206 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_config()  local
209 	ret = clk_prepare_enable(imx->clk_ipg);  in imx_pwm_config()
213 	ret = imx->config(chip, pwm, duty_ns, period_ns);  in imx_pwm_config()
215 	clk_disable_unprepare(imx->clk_ipg);  in imx_pwm_config()
222 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_enable()  local
225 	ret = clk_prepare_enable(imx->clk_per);  in imx_pwm_enable()
229 	imx->set_enable(chip, true);  in imx_pwm_enable()
236 	struct imx_chip *imx = to_imx_chip(chip);  in imx_pwm_disable()  local
238 	imx->set_enable(chip, false);  in imx_pwm_disable()
240 	clk_disable_unprepare(imx->clk_per);  in imx_pwm_disable()
278 	struct imx_chip *imx;  in imx_pwm_probe()  local
285 	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);  in imx_pwm_probe()
286 	if (imx == NULL)  in imx_pwm_probe()
289 	imx->clk_per = devm_clk_get(&pdev->dev, "per");  in imx_pwm_probe()
290 	if (IS_ERR(imx->clk_per)) {  in imx_pwm_probe()
292 				PTR_ERR(imx->clk_per));  in imx_pwm_probe()
293 		return PTR_ERR(imx->clk_per);  in imx_pwm_probe()
296 	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");  in imx_pwm_probe()
297 	if (IS_ERR(imx->clk_ipg)) {  in imx_pwm_probe()
299 				PTR_ERR(imx->clk_ipg));  in imx_pwm_probe()
300 		return PTR_ERR(imx->clk_ipg);  in imx_pwm_probe()
303 	imx->chip.ops = &imx_pwm_ops;  in imx_pwm_probe()
304 	imx->chip.dev = &pdev->dev;  in imx_pwm_probe()
305 	imx->chip.base = -1;  in imx_pwm_probe()
306 	imx->chip.npwm = 1;  in imx_pwm_probe()
307 	imx->chip.can_sleep = true;  in imx_pwm_probe()
310 	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);  in imx_pwm_probe()
311 	if (IS_ERR(imx->mmio_base))  in imx_pwm_probe()
312 		return PTR_ERR(imx->mmio_base);  in imx_pwm_probe()
315 	imx->config = data->config;  in imx_pwm_probe()
316 	imx->set_enable = data->set_enable;  in imx_pwm_probe()
318 	ret = pwmchip_add(&imx->chip);  in imx_pwm_probe()
322 	platform_set_drvdata(pdev, imx);  in imx_pwm_probe()
328 	struct imx_chip *imx;  in imx_pwm_remove()  local
330 	imx = platform_get_drvdata(pdev);  in imx_pwm_remove()
331 	if (imx == NULL)  in imx_pwm_remove()
334 	return pwmchip_remove(&imx->chip);  in imx_pwm_remove()