101 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_request()  local
103 	return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_request()
108 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_free()  local
110 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_free()
113 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_default_ps()  argument
119 	sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_calculate_default_ps()
123 	cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_default_ps()
129 		fpc->clk_ps = 1;  in fsl_pwm_calculate_default_ps()
134 		fpc->clk_ps = ratio;  in fsl_pwm_calculate_default_ps()
139 		fpc->clk_ps = ratio;  in fsl_pwm_calculate_default_ps()
148 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_cycles()  argument
153 	c = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_cycles()
159 		do_div(c0, (1 << fpc->clk_ps));  in fsl_pwm_calculate_cycles()
162 	} while (++fpc->clk_ps < 8);  in fsl_pwm_calculate_cycles()
167 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_period_cycles()  argument
173 	ret = fsl_pwm_calculate_default_ps(fpc, index);  in fsl_pwm_calculate_period_cycles()
175 		dev_err(fpc->chip.dev,  in fsl_pwm_calculate_period_cycles()
181 	return fsl_pwm_calculate_cycles(fpc, period_ns);  in fsl_pwm_calculate_period_cycles()
184 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_period()  argument
190 	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,  in fsl_pwm_calculate_period()
193 		fpc->cnt_select = FSL_PWM_CLK_SYS;  in fsl_pwm_calculate_period()
197 	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_calculate_period()
198 	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_calculate_period()
208 	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);  in fsl_pwm_calculate_period()
210 		fpc->cnt_select = m0;  in fsl_pwm_calculate_period()
214 	fpc->cnt_select = m1;  in fsl_pwm_calculate_period()
216 	return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);  in fsl_pwm_calculate_period()
219 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_duty()  argument
226 	regmap_read(fpc->regmap, FTM_MOD, &val);  in fsl_pwm_calculate_duty()
236 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_config()  local
239 	mutex_lock(&fpc->lock);  in fsl_pwm_config()
246 	if (fpc->period_ns && fpc->period_ns != period_ns) {  in fsl_pwm_config()
247 		dev_err(fpc->chip.dev,  in fsl_pwm_config()
250 		mutex_unlock(&fpc->lock);  in fsl_pwm_config()
254 	if (!fpc->period_ns && duty_ns) {  in fsl_pwm_config()
255 		period = fsl_pwm_calculate_period(fpc, period_ns);  in fsl_pwm_config()
257 			dev_err(fpc->chip.dev, "failed to calculate period\n");  in fsl_pwm_config()
258 			mutex_unlock(&fpc->lock);  in fsl_pwm_config()
262 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,  in fsl_pwm_config()
263 				   fpc->clk_ps);  in fsl_pwm_config()
264 		regmap_write(fpc->regmap, FTM_MOD, period - 1);  in fsl_pwm_config()
266 		fpc->period_ns = period_ns;  in fsl_pwm_config()
269 	mutex_unlock(&fpc->lock);  in fsl_pwm_config()
271 	duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);  in fsl_pwm_config()
273 	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),  in fsl_pwm_config()
275 	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);  in fsl_pwm_config()
284 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_set_polarity()  local
287 	regmap_read(fpc->regmap, FTM_POL, &val);  in fsl_pwm_set_polarity()
294 	regmap_write(fpc->regmap, FTM_POL, val);  in fsl_pwm_set_polarity()
299 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)  in fsl_counter_clock_enable()  argument
303 	if (fpc->use_count++ != 0)  in fsl_counter_clock_enable()
307 	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,  in fsl_counter_clock_enable()
308 			   FTM_SC_CLK(fpc->cnt_select));  in fsl_counter_clock_enable()
310 	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
314 	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_counter_clock_enable()
316 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
325 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_enable()  local
328 	mutex_lock(&fpc->lock);  in fsl_pwm_enable()
329 	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);  in fsl_pwm_enable()
331 	ret = fsl_counter_clock_enable(fpc);  in fsl_pwm_enable()
332 	mutex_unlock(&fpc->lock);  in fsl_pwm_enable()
337 static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)  in fsl_counter_clock_disable()  argument
342 	if (fpc->use_count == 0)  in fsl_counter_clock_disable()
346 	if (--fpc->use_count > 0)  in fsl_counter_clock_disable()
350 	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0);  in fsl_counter_clock_disable()
352 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_counter_clock_disable()
353 	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_disable()
358 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_disable()  local
361 	mutex_lock(&fpc->lock);  in fsl_pwm_disable()
362 	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),  in fsl_pwm_disable()
365 	fsl_counter_clock_disable(fpc);  in fsl_pwm_disable()
367 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);  in fsl_pwm_disable()
369 		fpc->period_ns = 0;  in fsl_pwm_disable()
371 	mutex_unlock(&fpc->lock);  in fsl_pwm_disable()
384 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)  in fsl_pwm_init()  argument
388 	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_init()
392 	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);  in fsl_pwm_init()
393 	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);  in fsl_pwm_init()
394 	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);  in fsl_pwm_init()
396 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_init()
422 	struct fsl_pwm_chip *fpc;  in fsl_pwm_probe()  local
427 	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);  in fsl_pwm_probe()
428 	if (!fpc)  in fsl_pwm_probe()
431 	mutex_init(&fpc->lock);  in fsl_pwm_probe()
433 	fpc->chip.dev = &pdev->dev;  in fsl_pwm_probe()
440 	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,  in fsl_pwm_probe()
442 	if (IS_ERR(fpc->regmap)) {  in fsl_pwm_probe()
444 		return PTR_ERR(fpc->regmap);  in fsl_pwm_probe()
447 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");  in fsl_pwm_probe()
448 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {  in fsl_pwm_probe()
450 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_probe()
453 	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");  in fsl_pwm_probe()
454 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))  in fsl_pwm_probe()
455 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_probe()
457 	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");  in fsl_pwm_probe()
458 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))  in fsl_pwm_probe()
459 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_probe()
461 	fpc->clk[FSL_PWM_CLK_CNTEN] =  in fsl_pwm_probe()
462 				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");  in fsl_pwm_probe()
463 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))  in fsl_pwm_probe()
464 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_probe()
466 	fpc->chip.ops = &fsl_pwm_ops;  in fsl_pwm_probe()
467 	fpc->chip.of_xlate = of_pwm_xlate_with_flags;  in fsl_pwm_probe()
468 	fpc->chip.of_pwm_n_cells = 3;  in fsl_pwm_probe()
469 	fpc->chip.base = -1;  in fsl_pwm_probe()
470 	fpc->chip.npwm = 8;  in fsl_pwm_probe()
471 	fpc->chip.can_sleep = true;  in fsl_pwm_probe()
473 	ret = pwmchip_add(&fpc->chip);  in fsl_pwm_probe()
479 	platform_set_drvdata(pdev, fpc);  in fsl_pwm_probe()
481 	return fsl_pwm_init(fpc);  in fsl_pwm_probe()
486 	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);  in fsl_pwm_remove()  local
488 	return pwmchip_remove(&fpc->chip);  in fsl_pwm_remove()
494 	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);  in fsl_pwm_suspend()  local
497 	regcache_cache_only(fpc->regmap, true);  in fsl_pwm_suspend()
498 	regcache_mark_dirty(fpc->regmap);  in fsl_pwm_suspend()
501 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);  in fsl_pwm_suspend()
503 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_suspend()
504 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_pwm_suspend()
505 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_suspend()
513 	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);  in fsl_pwm_resume()  local
517 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);  in fsl_pwm_resume()
519 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_resume()
520 		clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_pwm_resume()
521 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_resume()
525 	regcache_cache_only(fpc->regmap, false);  in fsl_pwm_resume()
526 	regcache_sync(fpc->regmap);  in fsl_pwm_resume()