Lines Matching refs:RAPL_CPU
1082 #define RAPL_CPU(_model, _ops) { \ macro
1090 RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
1091 RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
1092 RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
1093 RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
1094 RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
1095 RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
1096 RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
1097 RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
1098 RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
1099 RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
1100 RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
1101 RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
1102 RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
1103 RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
1104 RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
1105 RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
1106 RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
1107 RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */