78 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_name()
79 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_name()
103 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_pin()
104 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_pin()
291 	unsigned pin = g->pin - pctl->desc->pin_base;  in sunxi_pconf_group_set()
388 	pin -= pctl->desc->pin_base;  in sunxi_pmx_set()
404 	struct sunxi_desc_function *desc =  in sunxi_pmx_set_mux()  local
409 	if (!desc)  in sunxi_pmx_set_mux()
412 	sunxi_pmx_set(pctldev, g->pin, desc->muxval);  in sunxi_pmx_set_mux()
424 	struct sunxi_desc_function *desc;  in sunxi_pmx_gpio_set_direction()  local
432 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);  in sunxi_pmx_gpio_set_direction()
433 	if (!desc)  in sunxi_pmx_gpio_set_direction()
436 	sunxi_pmx_set(pctldev, offset, desc->muxval);  in sunxi_pmx_gpio_set_direction()
460 	u32 set_mux = pctl->desc->irq_read_needs_mux &&  in sunxi_pinctrl_gpio_get()
461 			test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);  in sunxi_pinctrl_gpio_get()
526 	struct sunxi_desc_function *desc;  in sunxi_pinctrl_gpio_to_irq()  local
527 	unsigned pinnum = pctl->desc->pin_base + offset;  in sunxi_pinctrl_gpio_to_irq()
533 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");  in sunxi_pinctrl_gpio_to_irq()
534 	if (!desc)  in sunxi_pinctrl_gpio_to_irq()
537 	irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;  in sunxi_pinctrl_gpio_to_irq()
557 			pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_request_resources()
575 			      pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_release_resources()
581 	u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);  in sunxi_pinctrl_irq_set_type()
629 					      pctl->desc->irq_bank_base);  in sunxi_pinctrl_irq_ack()
639 	u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);  in sunxi_pinctrl_irq_mask()
656 	u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);  in sunxi_pinctrl_irq_unmask()
711 	struct sunxi_desc_function *desc;  in sunxi_pinctrl_irq_of_xlate()  local
718 	pin = pctl->desc->pin_base + base + intspec[1];  in sunxi_pinctrl_irq_of_xlate()
720 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");  in sunxi_pinctrl_irq_of_xlate()
721 	if (!desc)  in sunxi_pinctrl_irq_of_xlate()
724 	*out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;  in sunxi_pinctrl_irq_of_xlate()
734 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)  in sunxi_pinctrl_irq_handler()  argument
736 	unsigned int irq = irq_desc_get_irq(desc);  in sunxi_pinctrl_irq_handler()
737 	struct irq_chip *chip = irq_desc_get_chip(desc);  in sunxi_pinctrl_irq_handler()
738 	struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);  in sunxi_pinctrl_irq_handler()
741 	for (bank = 0; bank < pctl->desc->irq_banks; bank++)  in sunxi_pinctrl_irq_handler()
745 	if (bank == pctl->desc->irq_banks)  in sunxi_pinctrl_irq_handler()
748 	reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);  in sunxi_pinctrl_irq_handler()
754 		chained_irq_enter(chip, desc);  in sunxi_pinctrl_irq_handler()
760 		chained_irq_exit(chip, desc);  in sunxi_pinctrl_irq_handler()
791 	pctl->ngroups = pctl->desc->npins;  in sunxi_pinctrl_build_state()
800 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
801 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
813 				pctl->desc->npins * sizeof(*pctl->functions),  in sunxi_pinctrl_build_state()
819 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
820 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
839 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
840 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
874 		       const struct sunxi_pinctrl_desc *desc)  in sunxi_pinctrl_init()  argument
897 	pctl->desc = desc;  in sunxi_pinctrl_init()
900 				       IRQ_PER_BANK * pctl->desc->irq_banks,  in sunxi_pinctrl_init()
913 			    pctl->desc->npins * sizeof(*pins),  in sunxi_pinctrl_init()
918 	for (i = 0; i < pctl->desc->npins; i++)  in sunxi_pinctrl_init()
919 		pins[i] = pctl->desc->pins[i].pin;  in sunxi_pinctrl_init()
930 	pctrl_desc->npins = pctl->desc->npins;  in sunxi_pinctrl_init()
948 	last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;  in sunxi_pinctrl_init()
961 			    pctl->desc->pin_base;  in sunxi_pinctrl_init()
964 	pctl->chip->base = pctl->desc->pin_base;  in sunxi_pinctrl_init()
970 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_init()
971 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_init()
974 					     pin->pin.number - pctl->desc->pin_base,  in sunxi_pinctrl_init()
991 				 pctl->desc->irq_banks,  in sunxi_pinctrl_init()
999 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init()
1008 					     pctl->desc->irq_banks * IRQ_PER_BANK,  in sunxi_pinctrl_init()
1017 	for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {  in sunxi_pinctrl_init()
1025 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init()
1028 						pctl->desc->irq_bank_base));  in sunxi_pinctrl_init()
1031 						pctl->desc->irq_bank_base));  in sunxi_pinctrl_init()