39 	struct sh_pfc *pfc;  member
53 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
61 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
69 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
70 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
109 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
264 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
317 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
325 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
335 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
336 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
345 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
346 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
351 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
354 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
364 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
370 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
379 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
380 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
385 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
388 		dev_err(pfc->dev,  in sh_pfc_gpio_request_enable()
395 	if (!pfc->gpio) {  in sh_pfc_gpio_request_enable()
399 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
401 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
411 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
421 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
422 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
426 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
428 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
436 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
438 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
439 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
454 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
456 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
463 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
478 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
481 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
482 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
506 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
510 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
519 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
522 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
523 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
524 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
536 		if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)  in sh_pfc_pinconf_get()
539 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
540 		ret = pfc->info->ops->get_io_voltage(pfc, _pin);  in sh_pfc_pinconf_get()
541 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
561 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
569 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
576 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
579 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
580 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
581 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
590 			if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)  in sh_pfc_pinconf_set()
593 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
594 			ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);  in sh_pfc_pinconf_set()
595 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
620 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
621 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
638 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
643 	pmx->pins = devm_kzalloc(pfc->dev,  in sh_pfc_map_pins()
644 				 sizeof(*pmx->pins) * pfc->info->nr_pins,  in sh_pfc_map_pins()
649 	pmx->configs = devm_kzalloc(pfc->dev,  in sh_pfc_map_pins()
650 				    sizeof(*pmx->configs) * pfc->info->nr_pins,  in sh_pfc_map_pins()
655 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
656 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
669 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
674 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
678 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
679 	pfc->pinctrl = pmx;  in sh_pfc_register_pinctrl()
681 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
691 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
693 	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);  in sh_pfc_register_pinctrl()
700 int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)  in sh_pfc_unregister_pinctrl()  argument
702 	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;  in sh_pfc_unregister_pinctrl()
706 	pfc->pinctrl = NULL;  in sh_pfc_unregister_pinctrl()