Lines Matching refs:shift
278 u8 shift; in s3c64xx_irq_set_function() local
284 shift = pin; in s3c64xx_irq_set_function()
285 if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) { in s3c64xx_irq_set_function()
288 shift -= 8; in s3c64xx_irq_set_function()
291 shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC]; in s3c64xx_irq_set_function()
297 val &= ~(mask << shift); in s3c64xx_irq_set_function()
298 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
350 u8 shift; in s3c64xx_gpio_irq_set_type() local
363 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_type()
364 shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */ in s3c64xx_gpio_irq_set_type()
367 val &= ~(EINT_CON_MASK << shift); in s3c64xx_gpio_irq_set_type()
368 val |= trigger << shift; in s3c64xx_gpio_irq_set_type()
560 u8 shift; in s3c64xx_eint0_irq_set_type() local
573 shift = ddata->eints[irqd->hwirq]; in s3c64xx_eint0_irq_set_type()
574 if (shift >= EINT_MAX_PER_REG) { in s3c64xx_eint0_irq_set_type()
576 shift -= EINT_MAX_PER_REG; in s3c64xx_eint0_irq_set_type()
578 shift = EINT_CON_LEN * (shift / 2); in s3c64xx_eint0_irq_set_type()
581 val &= ~(EINT_CON_MASK << shift); in s3c64xx_eint0_irq_set_type()
582 val |= trigger << shift; in s3c64xx_eint0_irq_set_type()