71 	mask = readl(d->virt_base + reg_mask);  in exynos_irq_mask()
73 	writel(mask, d->virt_base + reg_mask);  in exynos_irq_mask()
86 	writel(1 << irqd->hwirq, d->virt_base + reg_pend);  in exynos_irq_ack()
112 	mask = readl(d->virt_base + reg_mask);  in exynos_irq_unmask()
114 	writel(mask, d->virt_base + reg_mask);  in exynos_irq_unmask()
155 	con = readl(d->virt_base + reg_con);  in exynos_irq_set_type()
158 	writel(con, d->virt_base + reg_con);  in exynos_irq_set_type()
190 	con = readl(d->virt_base + reg_con);  in exynos_irq_request_resources()
193 	writel(con, d->virt_base + reg_con);  in exynos_irq_request_resources()
223 	con = readl(d->virt_base + reg_con);  in exynos_irq_release_resources()
226 	writel(con, d->virt_base + reg_con);  in exynos_irq_release_resources()
276 	svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);  in exynos_eint_gpio_irq()
467 		pend = readl(d->virt_base + b->irq_chip->eint_pend  in exynos_irq_demux_eint16_31()
469 		mask = readl(d->virt_base + b->irq_chip->eint_mask  in exynos_irq_demux_eint16_31()
587 	void __iomem *regs = drvdata->virt_base;  in exynos_pinctrl_suspend_bank()
616 	void __iomem *regs = drvdata->virt_base;  in exynos_pinctrl_resume_bank()