146 	u32 val;  in msm_pinmux_set_mux()  local
161 	val = readl(pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
162 	val &= ~(0x7 << g->mux_bit);  in msm_pinmux_set_mux()
163 	val |= i << g->mux_bit;  in msm_pinmux_set_mux()
164 	writel(val, pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
213 static unsigned msm_regval_to_drive(u32 val)  in msm_regval_to_drive()  argument
215 	return (val + 1) * 2;  in msm_regval_to_drive()
229 	u32 val;  in msm_config_group_get()  local
237 	val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_get()
238 	arg = (val >> bit) & mask;  in msm_config_group_get()
262 		val = readl(pctrl->regs + g->io_reg);  in msm_config_group_get()
263 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
293 	u32 val;  in msm_config_group_set()  local
330 			val = readl(pctrl->regs + g->io_reg);  in msm_config_group_set()
332 				val |= BIT(g->out_bit);  in msm_config_group_set()
334 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
335 			writel(val, pctrl->regs + g->io_reg);  in msm_config_group_set()
358 		val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_set()
359 		val &= ~(mask << bit);  in msm_config_group_set()
360 		val |= arg << bit;  in msm_config_group_set()
361 		writel(val, pctrl->regs + g->ctl_reg);  in msm_config_group_set()
386 	u32 val;  in msm_gpio_direction_input()  local
392 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
393 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
394 	writel(val, pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
406 	u32 val;  in msm_gpio_direction_output()  local
412 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
414 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
416 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
417 	writel(val, pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
419 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
420 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
421 	writel(val, pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
432 	u32 val;  in msm_gpio_get()  local
436 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_get()
437 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
445 	u32 val;  in msm_gpio_set()  local
451 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_set()
453 		val |= BIT(g->out_bit);  in msm_gpio_set()
455 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
456 	writel(val, pctrl->regs + g->io_reg);  in msm_gpio_set()
548 	unsigned val, val2, intstat;  in msm_gpio_update_dual_edge_pos()  local
552 		val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
560 		if (intstat || (val == val2))  in msm_gpio_update_dual_edge_pos()
564 		val, val2);  in msm_gpio_update_dual_edge_pos()
573 	u32 val;  in msm_gpio_irq_mask()  local
579 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
580 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
581 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
594 	u32 val;  in msm_gpio_irq_unmask()  local
600 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
601 	val &= ~BIT(g->intr_status_bit);  in msm_gpio_irq_unmask()
602 	writel(val, pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
604 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
605 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
606 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
619 	u32 val;  in msm_gpio_irq_ack()  local
625 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
627 		val |= BIT(g->intr_status_bit);  in msm_gpio_irq_ack()
629 		val &= ~BIT(g->intr_status_bit);  in msm_gpio_irq_ack()
630 	writel(val, pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
644 	u32 val;  in msm_gpio_irq_set_type()  local
659 	val = readl(pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
660 	val &= ~(7 << g->intr_target_bit);  in msm_gpio_irq_set_type()
661 	val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
662 	writel(val, pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
669 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
670 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
672 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
673 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
676 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
677 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
680 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
681 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
684 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
685 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
690 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
694 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
695 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
698 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
699 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
702 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
705 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
706 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
711 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
717 	writel(val, pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
764 	u32 val;  in msm_gpio_irq_handler()  local
775 		val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_handler()
776 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()