161 	val = readl(pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
237 	val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_get()
262 		val = readl(pctrl->regs + g->io_reg);  in msm_config_group_get()
330 			val = readl(pctrl->regs + g->io_reg);  in msm_config_group_set()
358 		val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_set()
392 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
412 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
419 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
436 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_get()
451 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_set()
486 	ctl_reg = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_dbg_show_one()
552 		val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
554 		pol = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_update_dual_edge_pos()
558 		val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
559 		intstat = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_update_dual_edge_pos()
579 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
600 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
604 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
625 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
659 	val = readl(pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
669 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
775 		val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_handler()