Lines Matching refs:g
144 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
149 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
151 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
152 if (g->funcs[i] == function) in msm_pinmux_set_mux()
156 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
161 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
162 val &= ~(0x7 << g->mux_bit); in msm_pinmux_set_mux()
163 val |= i << g->mux_bit; in msm_pinmux_set_mux()
164 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
179 const struct msm_pingroup *g, in msm_config_reg() argument
189 *bit = g->pull_bit; in msm_config_reg()
193 *bit = g->drv_bit; in msm_config_reg()
198 *bit = g->oe_bit; in msm_config_reg()
222 const struct msm_pingroup *g; in msm_config_group_get() local
231 g = &pctrl->soc->groups[group]; in msm_config_group_get()
233 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
237 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
262 val = readl(pctrl->regs + g->io_reg); in msm_config_group_get()
263 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
285 const struct msm_pingroup *g; in msm_config_group_set() local
296 g = &pctrl->soc->groups[group]; in msm_config_group_set()
302 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
330 val = readl(pctrl->regs + g->io_reg); in msm_config_group_set()
332 val |= BIT(g->out_bit); in msm_config_group_set()
334 val &= ~BIT(g->out_bit); in msm_config_group_set()
335 writel(val, pctrl->regs + g->io_reg); in msm_config_group_set()
358 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
361 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
383 const struct msm_pingroup *g; in msm_gpio_direction_input() local
388 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
392 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
393 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
394 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
403 const struct msm_pingroup *g; in msm_gpio_direction_output() local
408 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
412 val = readl(pctrl->regs + g->io_reg); in msm_gpio_direction_output()
414 val |= BIT(g->out_bit); in msm_gpio_direction_output()
416 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
417 writel(val, pctrl->regs + g->io_reg); in msm_gpio_direction_output()
419 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
420 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
421 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
430 const struct msm_pingroup *g; in msm_gpio_get() local
434 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
436 val = readl(pctrl->regs + g->io_reg); in msm_gpio_get()
437 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
442 const struct msm_pingroup *g; in msm_gpio_set() local
447 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
451 val = readl(pctrl->regs + g->io_reg); in msm_gpio_set()
453 val |= BIT(g->out_bit); in msm_gpio_set()
455 val &= ~BIT(g->out_bit); in msm_gpio_set()
456 writel(val, pctrl->regs + g->io_reg); in msm_gpio_set()
470 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
485 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
486 ctl_reg = readl(pctrl->regs + g->ctl_reg); in msm_gpio_dbg_show_one()
488 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
489 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
490 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
491 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
493 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); in msm_gpio_dbg_show_one()
544 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
552 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
554 pol = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
555 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
556 writel(pol, pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
558 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
559 intstat = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_update_dual_edge_pos()
571 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
575 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
579 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
580 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
581 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
592 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
596 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
600 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_unmask()
601 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_unmask()
602 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_unmask()
604 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
605 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
606 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
617 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
621 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
625 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
626 if (g->intr_ack_high) in msm_gpio_irq_ack()
627 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
629 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
630 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
633 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
642 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
646 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
653 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
659 val = readl(pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
660 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
661 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
662 writel(val, pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
669 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
670 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
671 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
672 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
673 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
676 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
677 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
680 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
681 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
684 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
685 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
690 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
693 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
694 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
695 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
698 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
699 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
702 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
705 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
706 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
711 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
717 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
720 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
759 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
774 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
775 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_handler()
776 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()