305 	const struct tegra_xusb_padctl_lane *lane;  in tegra_xusb_padctl_pinmux_set()  local
309 	lane = &padctl->soc->lanes[group];  in tegra_xusb_padctl_pinmux_set()
311 	for (i = 0; i < lane->num_funcs; i++)  in tegra_xusb_padctl_pinmux_set()
312 		if (lane->funcs[i] == function)  in tegra_xusb_padctl_pinmux_set()
315 	if (i >= lane->num_funcs)  in tegra_xusb_padctl_pinmux_set()
318 	value = padctl_readl(padctl, lane->offset);  in tegra_xusb_padctl_pinmux_set()
319 	value &= ~(lane->mask << lane->shift);  in tegra_xusb_padctl_pinmux_set()
320 	value |= i << lane->shift;  in tegra_xusb_padctl_pinmux_set()
321 	padctl_writel(padctl, value, lane->offset);  in tegra_xusb_padctl_pinmux_set()
338 	const struct tegra_xusb_padctl_lane *lane;  in tegra_xusb_padctl_pinconf_group_get()  local
343 	lane = &padctl->soc->lanes[group];  in tegra_xusb_padctl_pinconf_group_get()
348 		if (lane->iddq == 0)  in tegra_xusb_padctl_pinconf_group_get()
351 		value = padctl_readl(padctl, lane->offset);  in tegra_xusb_padctl_pinconf_group_get()
353 		if (value & BIT(lane->iddq))  in tegra_xusb_padctl_pinconf_group_get()
376 	const struct tegra_xusb_padctl_lane *lane;  in tegra_xusb_padctl_pinconf_group_set()  local
382 	lane = &padctl->soc->lanes[group];  in tegra_xusb_padctl_pinconf_group_set()
391 			if (lane->iddq == 0)  in tegra_xusb_padctl_pinconf_group_set()
394 			regval = padctl_readl(padctl, lane->offset);  in tegra_xusb_padctl_pinconf_group_set()
397 				regval &= ~BIT(lane->iddq);  in tegra_xusb_padctl_pinconf_group_set()
399 				regval |= BIT(lane->iddq);  in tegra_xusb_padctl_pinconf_group_set()
401 			padctl_writel(padctl, regval, lane->offset);  in tegra_xusb_padctl_pinconf_group_set()