408 	struct st_gpio_bank *bank = gpio_range_to_bank(range);  in st_get_pio_control()  local
410 	return &bank->pc;  in st_get_pio_control()
706 static inline void __st_gpio_set(struct st_gpio_bank *bank,  in __st_gpio_set()  argument
710 		writel(BIT(offset), bank->base + REG_PIO_SET_POUT);  in __st_gpio_set()
712 		writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);  in __st_gpio_set()
715 static void st_gpio_direction(struct st_gpio_bank *bank,  in st_gpio_direction()  argument
739 			writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));  in st_gpio_direction()
741 			writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));  in st_gpio_direction()
747 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_get()  local
749 	return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));  in st_gpio_get()
754 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_set()  local
755 	__st_gpio_set(bank, offset, value);  in st_gpio_set()
768 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_direction_output()  local
770 	__st_gpio_set(bank, offset, value);  in st_gpio_direction_output()
778 	struct st_gpio_bank *bank = gpio_chip_to_bank(chip);  in st_gpio_get_direction()  local
779 	struct st_pio_control pc = bank->pc;  in st_gpio_get_direction()
798 		value = readl(bank->base + REG_PIO_PC(i));  in st_gpio_get_direction()
972 	struct st_gpio_bank *bank = gpio_range_to_bank(range);  in st_pmx_set_gpio_direction()  local
978 	st_pctl_set_function(&bank->pc, gpio, 0);  in st_pmx_set_gpio_direction()
979 	st_gpio_direction(bank, gpio, input ?  in st_pmx_set_gpio_direction()
1102 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime_packed()  argument
1108 	int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;  in st_pctl_dt_setup_retime_packed()
1138 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime_dedicated()  argument
1144 	int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;  in st_pctl_dt_setup_retime_dedicated()
1162 	int bank, struct st_pio_control *pc)  in st_pctl_dt_setup_retime()  argument
1166 		return st_pctl_dt_setup_retime_packed(info, bank, pc);  in st_pctl_dt_setup_retime()
1168 		return st_pctl_dt_setup_retime_dedicated(info, bank, pc);  in st_pctl_dt_setup_retime()
1175 					    struct regmap *regmap, int bank,  in st_pc_get_value()  argument
1178 	struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);  in st_pc_get_value()
1186 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,  in st_parse_syscfgs()  argument
1195 	int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;  in st_parse_syscfgs()
1197 	struct st_pio_control *pc = &info->banks[bank].pc;  in st_parse_syscfgs()
1201 	pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);  in st_parse_syscfgs()
1202 	pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);  in st_parse_syscfgs()
1203 	pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);  in st_parse_syscfgs()
1204 	pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);  in st_parse_syscfgs()
1209 	st_pctl_dt_setup_retime(info, bank, pc);  in st_parse_syscfgs()
1328 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_mask()  local
1330 	writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);  in st_gpio_irq_mask()
1336 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_unmask()  local
1338 	writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);  in st_gpio_irq_unmask()
1344 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_set_type()  local
1366 		comp = st_gpio_get(&bank->gpio_chip, pin);  in st_gpio_irq_set_type()
1373 	spin_lock_irqsave(&bank->lock, flags);  in st_gpio_irq_set_type()
1374 	bank->irq_edge_conf &=  ~(ST_IRQ_EDGE_MASK << (  in st_gpio_irq_set_type()
1376 	bank->irq_edge_conf |= pin_edge_conf;  in st_gpio_irq_set_type()
1377 	spin_unlock_irqrestore(&bank->lock, flags);  in st_gpio_irq_set_type()
1379 	val = readl(bank->base + REG_PIO_PCOMP);  in st_gpio_irq_set_type()
1382 	writel(val, bank->base + REG_PIO_PCOMP);  in st_gpio_irq_set_type()
1411 static void __gpio_irq_handler(struct st_gpio_bank *bank)  in __gpio_irq_handler()  argument
1417 	spin_lock_irqsave(&bank->lock, flags);  in __gpio_irq_handler()
1418 	bank_edge_mask = bank->irq_edge_conf;  in __gpio_irq_handler()
1419 	spin_unlock_irqrestore(&bank->lock, flags);  in __gpio_irq_handler()
1422 		port_in = readl(bank->base + REG_PIO_PIN);  in __gpio_irq_handler()
1423 		port_comp = readl(bank->base + REG_PIO_PCOMP);  in __gpio_irq_handler()
1424 		port_mask = readl(bank->base + REG_PIO_PMASK);  in __gpio_irq_handler()
1437 				val = st_gpio_get(&bank->gpio_chip, n);  in __gpio_irq_handler()
1440 					val ? bank->base + REG_PIO_SET_PCOMP :  in __gpio_irq_handler()
1441 					bank->base + REG_PIO_CLR_PCOMP);  in __gpio_irq_handler()
1448 			generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));  in __gpio_irq_handler()
1458 	struct st_gpio_bank *bank = gpio_chip_to_bank(gc);  in st_gpio_irq_handler()  local
1461 	__gpio_irq_handler(bank);  in st_gpio_irq_handler()
1507 	struct st_gpio_bank *bank = &info->banks[bank_nr];  in st_gpiolib_register_bank()  local
1508 	struct pinctrl_gpio_range *range = &bank->range;  in st_gpiolib_register_bank()
1517 	bank->base = devm_ioremap_resource(dev, &res);  in st_gpiolib_register_bank()
1518 	if (IS_ERR(bank->base))  in st_gpiolib_register_bank()
1519 		return PTR_ERR(bank->base);  in st_gpiolib_register_bank()
1521 	bank->gpio_chip = st_gpio_template;  in st_gpiolib_register_bank()
1522 	bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;  in st_gpiolib_register_bank()
1523 	bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;  in st_gpiolib_register_bank()
1524 	bank->gpio_chip.of_node = np;  in st_gpiolib_register_bank()
1525 	bank->gpio_chip.dev = dev;  in st_gpiolib_register_bank()
1526 	spin_lock_init(&bank->lock);  in st_gpiolib_register_bank()
1529 	bank->gpio_chip.label = range->name;  in st_gpiolib_register_bank()
1533 	range->npins = bank->gpio_chip.ngpio;  in st_gpiolib_register_bank()
1534 	range->gc = &bank->gpio_chip;  in st_gpiolib_register_bank()
1535 	err  = gpiochip_add(&bank->gpio_chip);  in st_gpiolib_register_bank()
1563 		gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,  in st_gpiolib_register_bank()
1568 		err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,  in st_gpiolib_register_bank()
1572 			gpiochip_remove(&bank->gpio_chip);  in st_gpiolib_register_bank()
1607 	int i = 0, j = 0, k = 0, bank;  in st_pctl_probe_dt()  local
1667 	bank = 0;  in st_pctl_probe_dt()
1671 			ret = st_gpiolib_register_bank(info, bank, child);  in st_pctl_probe_dt()
1675 			k = info->banks[bank].range.pin_base;  in st_pctl_probe_dt()
1676 			bank_name = info->banks[bank].range.name;  in st_pctl_probe_dt()
1683 			st_parse_syscfgs(info, bank, child);  in st_pctl_probe_dt()
1684 			bank++;  in st_pctl_probe_dt()