108 	void __iomem			*reg_base;  member
951 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);  in _rockchip_pmx_gpio_set_direction()
957 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);  in _rockchip_pmx_gpio_set_direction()
1380 	void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;  in rockchip_gpio_set()
1407 	data = readl(bank->reg_base + GPIO_EXT_PORT);  in rockchip_gpio_get()
1478 	pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);  in rockchip_irq_demux()
1502 			data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);  in rockchip_irq_demux()
1506 				polarity = readl_relaxed(bank->reg_base +  in rockchip_irq_demux()
1513 				       bank->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_demux()
1518 				data = readl_relaxed(bank->reg_base +  in rockchip_irq_demux()
1548 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);  in rockchip_irq_set_type()
1550 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);  in rockchip_irq_set_type()
1562 	level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);  in rockchip_irq_set_type()
1563 	polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_set_type()
1574 		data = readl(bank->reg_base + GPIO_EXT_PORT);  in rockchip_irq_set_type()
1607 	writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);  in rockchip_irq_set_type()
1608 	writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_set_type()
1705 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);  in rockchip_interrupts_register()
1706 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);  in rockchip_interrupts_register()
1709 		gc->reg_base = bank->reg_base;  in rockchip_interrupts_register()
1809 	bank->reg_base = devm_ioremap_resource(info->dev, &res);  in rockchip_get_bank_data()
1810 	if (IS_ERR(bank->reg_base))  in rockchip_get_bank_data()
1811 		return PTR_ERR(bank->reg_base);  in rockchip_get_bank_data()